Defect and Fault Tolerance in VLSI Systems; proceedings.
Defect and fault tolerance in VLSI systems; proceedings.
IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (20th: 2005: Monterey, CA) Ed. by Robert Aitken et al.
Computer Society Press
These proceedings of the October 2005 symposium include the 49 regular papers presented as well as 23 papers of a special interactive session. Along with the two general talks (on thinking "out of the box" in error tolerance and error tolerance in razor processors) general topics include field analysis and modeling, scan design and test data compression, reconfiguration, error correcting codes and circuits, fault detection and tolerance for sensor and flash memory, delay fault test and timing considerations, defect and fault tolerant design in QCA circuits, interconnect test, approaches for soft errors, online and concurrent fault detection, fault and error tolerant systems, test scheduling and software-based test, and testing and design for analog circuits. Five case studies are included.
([c] 2005 Book News, Inc., Portland, OR)
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|Publication:||SciTech Book News|
|Article Type:||Book Review|
|Date:||Dec 1, 2005|
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