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Decoupling strategies for PCBs: there's more to good decoupling than flooding your board with capacitors. The light caps and smart layout are essential.

It's no secret that most digital devices demand a high peak current as circuits switch immediately following a clock edge (FIGURE 1). For example, a 100 MHz device with an average current draw of 4 A may actually require 20 A of current during the first few nanoseconds of the clock cycle.

[FIGURE 1 OMITTED]

Obviously, including a 20 A power supply for this circuit will increase the size and cost of the final product. Less obviously, the series inductance of PCB traces and component pins may make it impossible for a monolithic power supply to respond quickly enough to satisfy instantaneous current demands. If insufficient current capacity is available to the device, it will experience some combination of voltage droop and ground bounce. These phenomena usually manifest as high-frequency noise.

Decoupling capacitors address these problems by providing a distributed source of operating current accessible via a low-impedance (i.e., low-inductance) path. As a practical matter, the decoupling capacitors serve to directly power dig ital devices, while the main power supply serves to recharge the capacitors. The key to the successful design of a capacitor decoupling network is choosing the right capacitors and using the right layout.

Using capacitors in decoupling applications requires an understanding of how a capacitor behaves. FIGURE 2a depicts an ideal capacitor. This capacitor acts as a perfect reservoir, delivering stored charge instantly and without any voltage drop. The impedance of an ideal capacitor decreases monotonically as frequency increases. Since most noise in digital systems tends to be high frequency (>50 MHz), the decreasing impedance curve suits the application perfectly.

[FIGURE 2 OMITTED]

Unfortunately, the behavior of a "real" capacitor is not that simple. FIGURE 2b shows a simplified model of a real capacitor. The physical construction of a capacitor introduces a series resistance, specified as effective series resistance (ESR), and a series inductance, specified as effective series inductance (ESL). The addition of these two parasitic effects results in the considerably different impedance curve shown in FIGURE 3.

[FIGURE 3 OMITTED]

The lowest point in the impedance curve is known as the self-resonant frequency. Engineers often try to choose capacitors with a self-resonant frequency close to the system's operating frequency. However, the parameters of real capacitors make this impractical as clock speeds exceed 100 MHz. The important thing to remember is that it is perfectly acceptable to operate decoupling capacitors above the self-resonant frequency, as long as the impedance at important frequencies remains low enough for that application.

Like any resistance, the ESR of a capacitor results in a voltage drop proportional to current. Because it is important to maintain a stable power supply voltage, low ESR capacitors (i.e., less than 200 milliohms) are desirable for decoupling applications. ESL determines how fast a capacitor can respond to changes in current. A low ESL capacitor will respond quickly to current demands--the most important job of a decoupling capacitor. Although ESR is the most widely advertised and scrutinized parameter of a capacitor, ESL is probably the most important. All the chip capacitors listed in TABLE 1 demonstrate good ESL characteristics.

Type I dielectric materials do not suffer from aging and have excellent temperature characteristics, but their low Dk make them impractical for use in decoupling applications. Type II dielectrics (e.g., X7R) are a better choice because of good aging (10% loss in 10 years) and temperature performance and high dielectric constants. Type III dielectrics have the highest Dk, but suffer from poor temperature characteristics (50 to 75% loss at temperature extremes) and 20% aging loss in 10 years.

Of the popular dielectrics, multilayered ceramic and plastic provide the best ESL and ESR characteristics. Ceramic capacitors are currently much easier to find and source than plastic. Tantalum is often used for bulk decoupling, but it is unsuitable for local decoupling duties.

Table 1 contains representative ESL values for various capacitor packages. The capacitor package is the primary determinant of capacitor ESL. A smaller package will usually provide better ESL than a larger package of the same capacitance. The very high ESL of non-SMT packages makes them unsuitable for decoupling tasks.

In general, the right strategy is to find the largest capacitance available in the smallest package. Be careful, though. The height of the capacitor package, which is often not clearly specified, can substantially affect ESL. As the overlapping ranges in Table 1 suggest, it is possible to select a package with a smaller footprint and end up with a higher overall ESL. Verify package height data and check manufacturers' impedance curves to determine the best combination of package and capacitance.

When laying out decoupling capacitors, the primary tenet is that inductance is the enemy. For the purpose of rough estimates, inductance in a 50 [OMEGA] FR-4 trace is approximately 9 pH per mil. Inductance for a single via is approximately 500 pH, although this can vary based upon via geometry.

Inductance is proportional to the distance traveled, so it is important to minimize the distance (i.e., trace length) between a digital device and the decoupling capacitor. Inductance is inversely proportional to width, so wide traces are better than narrow traces. Inductors in parallel decrease in value ([L.sub.t] = [L.sub.1] * [L.sub.2]/([L.sub.1] + [L.sub.2]), much like resistors.

Remember that current always travels in a loop. It is the length of the complete current loop that must be minimized. Decreasing the distance between a device power pin and the power side of a capacitor at the expense of the ground return path will yield no improvement in total inductance. That said, it is a matter of debate as to whether it is better to position the capacitor closer to the power pin, closer to the ground pin, or to position it evenly between the two pins. Some sources recommend placing the capacitor closest to the pin with the most distant reference plane.

Options for Capacitor Layout

Good layout is vitally important for an effective decoupling design. As indicated in Table 1, capacitors of less than 1 nH are readily available. Adding just 2 nH of inductance to your layout will effectively triple the ESL of the capacitor. FIGURE 4 demonstrates the shift in self-resonant frequency and increased impedance created by adding 2 nH of layout inductance to a 4.7 nF, 0.8 nH capacitor.

[FIGURE 4 OMITTED]

FIGURE 5 shows a handful of methods for placing and connecting decoupling capacitors. For clarity, the diagram focuses on the connection between the capacitor and the device power pin. The connection between the capacitor and the device ground pin is equally important and should be treated with equal care.

[FIGURE 5 OMITTED]

Figure 5a demonstrates what is perhaps the most common configuration for decoupling capacitors. The device power pin connects to a power via using a short breakout. A decoupling capacitor on the opposite side of the hoard shares the same via. Although this approach is often dictated by the availability of PCB real estate, it performs well and saves routing space by sharing vias between the chip and capacitor. The two vias alone will add around 1 nH of inductance. If the capacitor body is placed 0.050" away from the device pins, the 0.100" (minimum) round trip will add another 0.9 nH for a total of 1.9 nH. If ground and power pins do not align with the capacitor pads, or if the capacitor is placed at a right angle to the device pins, the round-trip trace length will necessarily be longer.

By using wider traces, Figure 5d illustrates a potential improvement over the configuration in Figure 5a. It is worth noting that via inductance is proportional to height and to the natural log of width. Although shortening vias with techniques such as backdrilling will improve performance, making them wider will provide very little improvement.

The layout configuration shown in Figure 5b demonstrates a potential for excellent performance. Because there is no via between the chip and capacitor, the added inductance of this layout is limited to the trace itself. If this approach is applied to both power and ground, and traces are kept short, this layout can add less than 1 nH of inductance to the decoupling circuit. Figure 5e shows a simple improvement by using wider traces. Be aware that manufacturing design rules may prevent placing the capacitor close enough to the device pins to take best advantage of this approach.

At first glance, the layout in Figure 5c appears undesirable because there are no traces connecting the device to the decoupling capacitor. Actually, both the device and the capacitor are connecting to the solid power and ground planes through the vias. With four vias in the current path, the decoupling circuit will have a minimum of 2 nH of inductance. However, the very wide reference planes will add almost no inductance over reasonable distances. This is a good layout to use when a decoupling capacitor cannot he placed within 0.060" or 0.070" of a device pad.

Figure 5f improves on this layout by using two vias in parallel for each connection. This will effectively halve the total inductance of the decoupling circuit. Using multiple vias in parallel will improve the performance of any layout, and should be done whenever space and plane integrity permit.

Multiple Capacitors

Because capacitances in parallel sum and inductances in parallel decrease, it can be beneficial to place two smaller capacitors of identical value in parallel in the place of a single larger capacitor. The end result is a similar capacitance and, assuming the packages were chosen carefully, a lower ESL.

A common practice to avoid is the use of more than one value of capacitor to provide local decoupling. Multiple capacitor values are used in an attempt to improve frequency response by blending two or more impedance curves. For example, in FIGURE 6, a 47 nF capacitor is used to decouple low frequencies while a 150 pF capacitor decouples high frequencies. At first inspection, we would expect that the two capacitors in parallel would produce the improved impedance curve highlighted in green.

[FIGURE 6 OMITTED]

Unfortunately, we would be wrong. This technique has significant problems in the intermediate frequencies between the two self-resonant points. As FIGURE 7 reveals, the combination of the two capacitors creates an anti-resonant peak. The source of the problem can be clearly seen in FIGURE 8: Placing the capacitors in parallel, along with their parasitic components, results in a classic "tank circuit."

[FIGURES 7-8 OMITTED]
TABLE 1. ESL Values for Various Capacitor Packages

PACKAGE SIZE ESL min (nH) ESL max (nH)

0402 0.54 1.90
0603 0.54 1.95
0805 0.70 1.94
1206 1.37 2.26
1210 0.61 1.55
1812 0.91 2.25
1815 0.98 1.96
Radial Package 6.0 15.0
Axial Package 12.0 20.0


JOE THOMPSON is president of Advanced Principles Group (advancedprinciples.com). He holds a master's degree in electrical engineering from Mississippi State University. He can be reached at joe@advancedprinciples.com.
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Title Annotation:printed circuit board components and design; Digital Design
Author:Thompson, Joe
Publication:Printed Circuit Design & Manufacture
Date:Oct 1, 2003
Words:1845
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