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Debug code for ARM Cortex-M3 MCUs.

ARM counts six large silicon suppliers as licensees for the Cortex-M3 processor core, which attests to its popularity. Microcontroller manufacturers license the Cortex-M3 core and its attendant debug-and-trace macrocells, called CoreSight. The CoreSight block includes many capabilities, and hardware and software engineers should know how to take advantage of them.


On a Cortex-M3, a debug-port (DP) block gives you access to the ARM core (for clarity, I'll call it the CPU) via either a JTAG or a serial-wire debug interface. Both offer the same debug capabilities, but the serial-wire interface requires fewer pins than a JTAG port. Engineers often refer to the serial-wire interface as a 1-pin interface, but the interface specifies as many as three signals, serial-wire output (SWO), serial-wire data I/O (SWDIO), and serial-wire clock (SWCLK).

"The debug-port block connects to the processor, but it also gives you direct access to memory," explained Javier Orensanz, product manager for debug and profiling tools at ARM. "So software downloads occur faster, and debug tools can access memory at the same time the CPU runs code. If you want to look at variables in memory, for example, the debugger can obtain this information with only a slight increase in the memory system's latency."

Depending on the manufacturer, a Cortex-M3 MCU also may include an eEmbedded-trace Trace Macrocell (ETM), which generates instruction-trace packets as either serial data or as parallel data on four data lines. The ETM lets tools, such as the ULINKpro and Microcontroller Development Kit - MDK - from Keil, run a long-term trace so you can view the "history" of instructions executed by the CPU.

"Then you can generate profile and code-coverage reports," explained Orensanz. "You don't have to 'instrument' your code when you use this hardware capability." Instrumenting code involves placing a few extra instructions in the code to save information in locations you can access later. Because the instrumenting process adds code, it has an effect on performance and timing, and sometimes on the behavior of the software.

"Customers who have any concerns about code safety and reliability can take advantage of the profiling capabilities of the Cortex-M3 CPU and third-party development software," said Jean Anne Booth, director of worldwide Stellaris marketing at Texas Instruments. "These people must prove their code executed all paths through a program. The serial-wire trace [SWT] in a Cortex-M3 core gives you instruction information every few cycles, and when watchpoint matches occur. It doesn't give you a list of every executed instruction, but by using your object code software tools you can reconstruct what occurred between the samples."

The Cortcx-M3 also provides an instrumentation-trace macrocell (ITM), a central part of the debug logic. "The ITM provides selected trace data over a low speed access port," said Tomas Hedqvist, global account manager at IAR Systems. "But you don't need a separate external trace probe. A probe such as our J-Link handles the trace functions. The ITM provides 32 stimulus registers, so application software can create short packets of information to transmit via these registers to debug-and-trace software through the SWO output. Software, such as C-SPY on a host PC, sorts packets from the 32 possible- registers and displays information for you that relates to specific sections of your code."


"A simple write instruction in your code quickly transfers information to one of the 32 channels," continued Hedqvist. "Unlike a C-language printf function, the write instruction requires little CPU overhead because the CPU does not call a lengthy UART or Ethernet routine to output the register data. Our IAR Embedded Workbench tools use one register to implement a non-intrusive 'printf type of operation that outputs messages to the terminal I/O window on the host PC. And as an option, the channel can timestamp each packet it sends." A C-language printf function would dramatically increase the size of your object code, too.

"Another ARM component, the data watchpoint and trace (DWT), collects information from the system buses and generates events that the ITM time stamps and transmits on the SWO channel," explained Hedqvist. "Four independent comparators or watchpoints can trigger an event based on an address or data match. You can set a data 'breakpoint,' for example, so an event that affects data in a watched address triggers an event.

To view the expanded online version of Jon's article, visit

By Jon Titus, Senior Technical Editor
COPYRIGHT 2010 Advantage Business Media
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Title Annotation:Titus on Embedded
Author:Titus, Jon
Publication:ECN-Electronic Component News
Date:Aug 1, 2010
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