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DIGITAL PHASE-SENSITIVE DETECTOR (PSD) AS ACCUMULATOR-SAMPLER AND ITS IMPLEMENTATION IN FPGA.

Byline: S. Talha Ahsan and H. McCann

ABSTRACT: Phase-sensitive detection (PSD) is an established measurement technique for noisy signals. More recently, digital implementation of PSD using FPGA (Field Programmable Gate Array) or processor is becoming norm. This paper presents an FPGA-based digital PSD system, which is incorporated in a multi- channel bio-medical EIT instrument. In the paper, digital PSD has been analyzed using time- and frequency- domain methods of signal processing theory and a new interpretation of digital PSD in terms of accumulator - sampler has been given. Regarding design and implementation of the FPGA-based digital PSD system, two important issues of number of digitized waveform samples for use in PSD calculation and finite word length effect on PSD precision have been explored. Test results of the EIT instrument incorporating this digital PSD system have shown good noise performance, achieving an overall SNR of almost 80 dB at the high data- capturing rate of 100 frames/sec. The instrument also showed measurement capability to resolve large conductivity changes over very small spatial regions.

Key Words: accumulator, FPGA, matched filter, noise, precision, PSD, SNR1. INTRODUCTIONPhase-Sensitive detection (PSD) is a technique used ininstrumentation and measurement systems, to extract the characteristic(s) of a signal buried in noise [1]. This technique is used in, for example, electrical impedance tomography (EIT) systems [2] to recover the amplitude and phase information of the measured sinusoidal voltage signal, which could be buried in random noise. PSD also has other names in the literature, such as lock-in detection, synchronous detection and coherent/balanced demodulation. Mathematically, PSD is a special case of the correlation principle [1].

ANALOGUE AND DIGITAL PSDTraditionally, an analogue PSD circuit (figure 1) comprises aswitching amplifier (whose gain is switched between +B andB) followed by a low-pass filter [3,4]. Switching of the amplifier gain is controlled by a reference signal having the same frequency (fc) as that of the input signal, Vin, whose amplitude A is the information to be extracted. The two signals, input and reference, have to be phase-locked, with phase difference , which would not necessarily be zero. The switching amplifier effectively acts as a synchronous full- wave rectifier for Vin, or as an analogue multiplier multiplying the input signal Vin with the square-wave reference signal. The low-pass filter, following the switching amplifier, extracts Vout, the dc component of the amplifier's output signal.The main disadvantage of the switching-based analogue PSD is that the odd harmonic components present in the square-wave signal can be potentially down-converted to dc and subsequently added into the otherwise correct dc component at the amplifier output, hence causing an error. For its resolution, modified version of analogue PSD uses analogue multiplier instead of switching amplifier with thereference signal being a sinusoid instead of square-wave. Its close counterpart is the analogue matched filter, in which an analogue multiplier, having sinusoidal reference and the measured signal as the two inputs, is followed by an integrator-sampler [5]. The analogue matched filter provides maximum SNR improvement when detecting signals in Gaussian noise [2].It can be shown mathematically that Vout for both types of analogue PSD mentioned above is proportional to AB cos. This PSD result can be interpreted and utilised in many ways. For example, if is known and/or constant, then this output dc value is proportional to the amplitude information (A) of the input signal, as B is known beforehand. On the other hand, if A is known and/or constant, then this output dcvalue is proportional to the cosine of the phase difference between the input and reference signals. Furthermore, this output dc value is proportional to that component of the input signal which is in phase with the reference signal; hence the term in-phase (I) component Vout,I.In cases where both A and are unknown and varying,then another PSD result is required. Thus, another PSD circuit, using a reference signal shifted by 900 from previous I-case, is used. This gives an output of the low-pass filter which would be proportional to AB sin. It is called quadrature-phase (Q) component Vout,Q. These two PSD circuits make up what is called an I/Q demodulator and,using their two dc output values Vout,I and Vout,Q, both the amplitude (A) and phase () information of the input signal Vin is calculated.The use of analogue PSD, of both gain-switching andanalogue-multiplier types, has problems [3, 6] in terms of noise, dc offset error, inaccurate matching of the I and Q arms of the I/Q demodulator, limited rejection by theanalogue low-pass filter, harmonic distortion etc. With the development of technology, digital alternatives of analogue matched filtering and analogue PSD started appearing, e.g. [7, 8]. It was proposed that the digital matched filter would provide an improvement in SNR over the analogue matched filter and a digital demodulator based on matched filtertheory would give the best SNR, besides being easy to modify [3, 5]. This triggered the use of digital PSD in the forthcoming EIT systems, which has now become a steady trend, e.g. [2,9] and [10, 11] have used DSP, Microprocessor and FPGA chips respectively to implement digital PSD. With the growth of the dsp techniques, digital PSD is now frequently implemented in the wide-ranging areas ofinstrumentation and tomography; see [12-16]. Recently, anew digital PSD system of switching type has been proposedIn the case of digital PSD, the two dc outputs Vout,I and Vout,Q can be shown mathematically as in equations 1 and 2. The constant K would represent the overall scaling factor as the analogue voltage actually measured is processed through each of the I and Q arms to ultimately reach the output of the low-pass filter.EquationThese two dc output values can be used to calculate theamplitude (A) and phase () of the input signal.This paper presents a digital PSD system implemented inFPGA. This digital PSD system has been incorporated ineach of the 35 parallel voltage-measurement channels of the bio-medical EIT instrument fEITER (functional Electrical Impedance Tomography of Evoked Responses) built at the University of Manchester [11]. The aim of fEITER is to achieve brain function imaging at sub-second time-scales,with the measurement sensitivity of around 80 dB at the highdata-capturing rate of 100 frames/sec. Firmware loaded on a Xilinx Virtex-4 SX35 FPGA performs the EIT operation, including the PSD calculation. Design and implementation of this FPGA-based PSD system are discussed in Sections 3 and 4.

2. TIME- AND FREQUENCY-DOMAIN ANALYSIS OF DIGITAL PSDThis section presents time- and frequency-domain analysisof digital PSD using a Matlab-based example. The simulated signal used here for PSD calculation is similar to the measured signal of the practically-implemented FPGA-based system.Following two digital PSD equations respectively are usedto implement the I and Q arms of the I/Q demodulator, in a processor or FPGA chip.used in PSD. In this example, value of L is 200. The signals yRefSine[n] and yRefCosine[n], the in-phase and quadrature-phase reference signals, are sinusoids of frequency 10 kHz, sampled at 500 kS/s and occupying the dynamic range of 16 bits, as in the practically implemented digital PSD system discussed later.The dc level of the digitised sinusoid, Adc = 32768Amplitude of the digitised sinusoid, G = 16384Phase-shift in the sinusoid, F = p / 3

A time- and frequency-domain based analysis of the PSDprocess involving these signals follows.Having L samples of these three signals is equivalent to implementing windowing i.e. time-domain multiplication of the three sinusoidal signals of frequency 10 kHz, with rectangular time-window function. As a result, the frequency spectrum of the rectangular time-window function is shiftedto 10 kHz. In the frequency spectrum of this up-shifted function, the centre peak-to-null width of the main lobe [18For window length L of 200 and Nyquist frequency of 250 kHz (corresponding to the sampling rate of 500 kS/s), this main lobe width is 2.5 kHz. Ideally, this bandwidth should be as small as possible. This would mean larger L, consequently increasing the 'cost' of digital implementation of PSD, as more number of samples would need to be processed.In the PSD process, two product sequences pI[n] and pQ[n]are calculated thus:EquationFigure 2 shows the magnitude frequency spectrum of pI[n], which is a result of the frequency-domain periodicconvolution between the spectra of yRefSine[n] and s[n]. Similarly, figure 3 shows the magnitude frequency spectrumof pQ[n], which is a result of the frequency-domain periodic convolution between the spectra of yRefCos[n] and s[n].The final summation sub-processes of equations 3 and 4 can be explained as follows [19, 20]. The L-point DiscreteFourier Transform (DFT) [18] of the signal pI[n] (of equation 3 is calculating zero frequency component of the L- point DFT of pI[n]. Thus the amplitude of the zero- frequency component in the plot of figure 2, viz. 2.6843 x1010, is the final PSD result of the I-arm zI of equation 3.Similarly, equation 4 is calculating zero frequencycomponent of the L-point DFT of the signal pQ [n] (of equation 11). Consequently, the amplitude of the zero- 1010, is the final PSD result of the Q-arm zQ of equation 4.2.1 Interpretation using Accumulator-SamplerAnother, new, interpretation of the final summation sub-process of equations 3 and 4 is that the summer is equivalent to an accumulator-sampler cascade. Its operation can be explained in time- and frequency-domains separately.

2.1.1 Time-domain interpretation ofAccumulator-Sampler:The input to the L-point accumulator is the signal pI[n]. The output of the accumulator pIacc[n] is the time-domain convolution (equation 14) of pI[n] and h[n]. The function h[n] is the impulse response of accumulator, which is a rectangular pulse of L samples having unity amplitudes.Figure 4 shows the output signal of the accumulator pI acc[n], comprising 2L-1 samples. The next stage of sampler picks only one sample of pI acc[n]. It is that sample of the convolution result when both functions pI[n] and h[n] in their convolution operation are fully overlapping. This happens when n = L-1 in equation 14, which then becomes equation 3. Thus the output of the sampler is the sample number L-1=199 of pI acc[n]; this is the final PSD result ofthe I-arm viz. zI = 2.6843 x 1010, as shown in figure 4. It isrelevant to mention here that equation 3 can also be

interpreted as implementing the digital matched filtering, as the signal yRefSine[n] comprises 4, i.e. integer, no. of cycles; thus yRefSine[n] can also be considered as the impulse response of the filter matched with the measured signal s[n].

2.1.2 Frequency-domain interpretation ofAccumulator-Sampler:The output of the accumulator in frequency-domain (figure5) is a result of multiplication of the magnitude frequency spectrum of the input pI[n] (figure 2) and magnitude frequency response of the accumulator. The accumulator part is followed by the sampler part, which extracts the zero- frequency component of this product, yielding the single number zI as the PSD result. Similarly considering the quadrature-phased PSD calculation, the same time- and frequency-domain interpretations can be given for equation4, using figures 6 and 7.These figures show the output signal of the accumulator pQ acc[n] in time- and frequency-domain respectively.The magnitude frequency response of the accumulator hasnulls at the integer multiples of 2.5 kHz, which is the ratio of the signal frequency (10 kHz) and the integer number of cycles (4) of the measured signal [6] being used in the PSD. This choice of an integer number of cycles of the measuredsignal for use in the PSD calculation thus ensures that the PSD reference signal has no dc component, which if present would invalidate the PSD calculations.The accuracy of the final PSD results can be checked against the known amplitude and phase values of the unipolar signal. Based on equations 1 and 2, the amplitude (A) and phase () values of the measured unipolar signal can be calculated as followsEquationK is the product of the overall conversion factor as the phase- and dc-level-shifted sinusoidal signal (s[n] of equation 7) is processed through the various sub-stages of PSD operation. In this Matlab-based example, the value of K is simply L, i.e. the number of samples used in the PSD operation. In a hardware-implemented system, K would be a product of L and various other gain/conversion factors as the signal is processed through the system (see section 3.2).Using zI, zQ, K and B as 2.6843x1010, 4.6493x1010, 200 and 32767 respectively in equation 15 yields A = 16384,which is equal to G, i.e. the amplitude of the example signal s[n]. Similarly, equation 16 gives = p/3 which is equal to the original phase shift in s[n].3. TWO IMPORTANT ISSUESIN DIGITAL IMPLEMENTATION OF PSDIn the design and implementation of the FPGA-based digitalPSD system, following two aspects were important in relation to the precision of the final PSD result.

3.1 Number of waveform samples used in digital PSDcalculationIn an ADC-based digital measurement system (figure 8), theoverall SNR (in dB) of the measurement stage can be described as [21]where:B = ADC resolution in bits (16 in the system presented here)FFS = fraction of the full-scale range of the ADC being used(1 here)fs = ADC sampling rate (500 kHz here)fs /2 is the Nyquist frequency of the ADC sampling processBW = Bandwidth of the final output

The last term in equation 17 (the ratio Nyquist frequency/bandwidth) has been called "process gain" by Kester and Bryant [21] and is critical. Till the output of the ADC, this factor has zero value, i.e. log of unity, as the occupied bandwidth of the signal, set by the anti-aliasing filter, is the same as the Nyquist frequency fs/2. However, the process gain increases after the PSD process. This is because the bandwidth of the signal after the PSD process is reduced, in inverse relationship with the number of samples L used in the PSD process, as discussed in section 3. Thus, every quadrupling in L results in the quadrupling of the ratio Nyquist frequency/bandwidth, and consequently in an increase of 6.02 dB in SQNR, i.e. an improvement of 1 bit in effective bit resolution [2, 6]. Thus, the factor of "process gain" contributing to the overall SNR of the measurement system is directly dependent on the number of samples L used in the PSD process.

The fact that every quadrupling in L results in an increase of 6.02 dB in the overall SNR was tested practically by developing two different versions of the FPGA firmware to implement the PSD operation on 1 and 4 cycles of the measured sinusoid. The final measurements showed an improvement of almost 5 dB in the achieved SNR when 200 samples from 4 cycles, instead of 1 cycle having 50 samples, were used. Hence for final implementation of the FPGA- based PSD system, L was selected as 200.

3.2 Finite word length effect on PSD PrecisionIn dsp implementations, increase in the number of bitsrequired to store the results of addition and multiplication operations must be controlled. This increase means more cost and, in an FPGA, more usage of FPGA resources, resulting in higher power consumption. On the other hand, the usage of a finite number of bits for the results of dsp calculation introduces other errors. These errors can be of overflow, round-off or truncation types, and have been given various names in dsp literature like finite word- length / register-length effect, bit-resolution effect or dsp noise [22]. The remedy is to use sufficiently long words to store results. In the FPGA-implemented PSD system presented here, there are various stages where usage of a finite number of bits would potentially result in finite word length errors. A careful analysis was required to assess the optimal number of bits to be used. Figure 9 shows the block diagram of the I or Q arm of the PSD algorithm, as implemented in each of the 35 measurement channels in the 'Xtreme DSP' slice of the Virtex-4 SX35 FPGA, along with the bit-resolutions actually used. In this figure, Xin is the measured unipolar sinusoidal signal coming from the 16-bit ADC, while XRef is the reference sinusoid coming from the look up table. As each Xtreme DSP slice comprises an 18 x 18 multiplier, an adder and a 48-bit accumulator [23], the need for the 17x16 multiplication, taking place in the PSD module, is provided for. No product needs to be rounded off and hence there is no round-off error before the accumulation stage.The number of bits (Paccmln) allocated for storing the final accumulation result of PSD required careful evaluation. This evaluation would tell whether the 48 bit accumulator in the Xtreme DSP slice is sufficient. It was also very important that Paccmln should not be much more than the actual requirement, since only the 16 most significant bits had to be picked out of the accumulator, as per the system specs. This meant that the final Vout,I and Vout,Q results would effectively be the accumulation result divided by 2Paccmln -16. In order to keep the SQNR of these final results above 80 dB, the valueof Paccmln had to be such that the result after this division would occupy at least 14 bits, giving 86 dB SQNR. In such a case, the accumulation result would occupy Paccmln-1 or Paccmln-2 bits.Here is how the value of Paccmln was evaluated. The PSDoperation took place over 200 samples; hence theaccumulation result of 200 products (each having bit resolution of 33 bits) would occupy Paccmln = 33 + P bits. If the two signals being multiplied in the PSD calculation had been occupying the full dynamic range of 16-bits in all of their samples, e.g. considering both signals as square-wave, the value of P would be log2(200)=7.64 bits. However, as both of the signals being multiplied are sinusoids, not square-waves, P would be less than 7.64. This meant that Paccmln could be expected to be around or less than 40 bits.The final selection of Paccmln was done empirically. Threedifferent PSD firmware versions, having Paccmln of 39, 38 and37, were used for measurement, and the captured data wasanalysed to assess the occupation range of the calculated Vout,I and Vout,Q values. With reference to equation 15 (where K = 10.2, being a product of L and three other gain/conversion factors as the signal was processed through the digital measurement system, viz. conversion factor between ADC input and output, gain of the instrumentation amplifier used and scaling factor due to bit truncation whenpicking 16 MSBs out of Paccmln), the value of precision in the measurement was 5.97, 11.93 and 23.87 V, for Paccmln = 37,38 and 39 bits respectively. These precision values arevisible in figure 10 (a), (b) and (c).More experiments were conducted with these three PSD firmwares to assess the amount of various types of noise present in the measured voltages and the role of the selected Paccmln in this regard. Finally, Paccmln was decided to be set at38-bit. With this value of Paccmln, there would not be anoverflow error in the accumulation result, as the accumulatorsize in the 'Xtreme DSP' slice is 48-bit. The only source of

error in the accumulation result would be the picking of 16MSBs from the Paccmln-bit result, i.e. truncation error.

4. PSD SYSTEM DEVELOPMENT AND IMPLEMENTATIONThis digital PSD system is incorporated in the 35 parallelvoltage-measurement channels of the EIT instrument fEITER, through the firmware loaded on the Xilinx Virtex-4SX35 FPGA [11, 24]. On the measurement side, the measured EIT voltages, for each of the 35 channels, are sampled by the 16-bit unipolar ADC at 500 kS/s, providing50 samples for each of the 5 cycles of the injected current. The PSD module implements PSD process over last 4 cycles, i.e. 200 samples, of every new current injection; first cycle is let pass for current settling. A look-up table comprising 200 samples is used for each of the two, in-phase and quadrature-phase, reference signals in the PSD module.The PSD code was first developed in Matlab and fine- tuned using Matlab-generated sinusoids of different frequencies, phase-shift and amplitude. After finalisation of the code, its VHDL version was developed and incorporated in the full system firmware. The number of bits allocated to the final PSD result in the VHDL code required careful selection, as explained above in section 3. To verify the final in-phase and quadrature values, Vout,I and Vout,Q, obtained from the PSD calculations, various test-vectors were pasted in the VHDL code to act as input signals, the test vectors having already been verified in Matlab simulation.

Usage of FPGA ResourcesApproximately 40 % of the 15360 slices of the Virtex-4SX35 FPGA are taken by the 35 channel PSD module. Some usage of these slices occurs in the two look up tables, of 200 samples each, of the PSD reference signals. These 400 samples are stored in 400 16-bit registers; thus only this storage takes up 400 i.e. 2.6 % slices. Further logic resources are used for connecting these registers to all of the 35 PSD channels. The core of the PSD calculation, viz. the multiply- accumulate operation, is implemented in 70 of the'XtremeDSP' slices available in the Xilinx Virtex-4 SX35FPGA, as two DSP-slices implement the multiply- accumulate arms of I and Q demodulation separately, for each of the 35 channels.5. EIT INSTRUMENT TESTS AND RESULTSAs is the routine for testing of EIT instruments, tank testswere conducted to assess the overall instrument's performance, with the above mentioned PSD firmware incorporated in the complete fEITER system. Results for some early and numerous later-conducted tests were reported in [25, 26] and [27] respectively. These tests mainly used cylindrical and head-like tanks containing a homogeneous saline solution of (typical) conductivity 500S/cm, through which polar current injection patterns were passed. In one example of head-like phantom tests with homogeneous saline solution, differential voltage measurements on adjacent electrodes displayed typical SNR values near 80 dB, with some reaching 90 dB and beyond (Figure 11).For two different experiments with reference salinesolutions, two plots of in-phase voltage components (Vout,I) measured on one of the channels are shown in figure 12. As explained in section 3.2 above, firmware with Paccmln = 38 bits was used. (The consequent 12 V measurement precision, i.e. the variation over 1 code, is visible in the plots.) The measurements shown range over, not 1 but, 4-5 codes. Thus the dominant noise in these measurements is not quantisation noise. Rather it is the noise contributed by other sources like external pick up, disturbance in the subject medium and intrinsic noise in the analogue electronics.This other noise is well above the level of the quantisation noise determined by Paccmln = 38 bits.Continuing with the tank tests, various objects such asmetallic or insulating rods, or sponges prepared in solutions of various conductivities, were placed in the baseline solution to introduce inhomogeneity during EIT data capture. These resulted in changes in measured voltages, from pre- to post-perturbation condition, due to the changes in the conductivity and/or permittivity of the medium inside the tank. For one such experiment, Figure 13(a) shows the plot of absolute changes in voltage magnitudes for all EIT measurement indices (i.e. combinations of the two separate pairs of electrodes, used for current injection and voltage measurement). One of these measurement indices, viz. no.166, corresponding to current injection at electrode pair 7-15 and voltage measurement at electrode pair 11-12, has got a relatively low value of voltage change viz. 44.9 V (shown as red-coloured in the plot of figure 13(a)). Figure 13(b) shows its time-based plot, over one minute, of the voltage magnitudes. This plot shows that it is nearing the noise limit, with the measured change in voltage magnitude slightly higher than the noise level. The plot still shows a well- resolved change of 0.162 %. This is the typical case of having 'detectable' and 'non-detectable' voltage changes. The signal shown in figure 13(b) is still detectable. But for those measurement indices in figure 13(a) having smaller voltage values, the signal changes would not be detectable as these will be buried in noise. This type of test explores the capability of the EIT instrument to resolve inhomogeneities of very small spatial extent, though of high conductivity contrast. Results of these and similar other tests demonstrated the fEITER system's measurement capability to resolve easily the cases where large conductivity changes occur over very small spatial regions within the subject.Test results using precision resistor wheel have beenreported in [11]. Results of hospital tests on humans have been reported in [11, 24, 28, 29, 30].

6. CONCLUSIONThis paper presents a digital PSD system implemented inFPGA, which is incorporated in a multi-channel bio-medical EIT instrument. In the paper, first a Matlab-based case of digital PSD has been analyzed using time- and frequency- domain methods of signal processing theory and a new interpretation of digital PSD in terms of accumulator- sampler has been given. The simulated signal used therein is similar to the measured signal of the practically- implemented FPGA-based system. Then the design and implementation of the FPGA-based digital PSD system has been discussed. Two important issues, viz. number of digitized waveform samples for use in PSD calculation and number of bits allocated for storage of digital results, have been explored, both of which ultimately affect the precision of the final PSD result. The analysis to evaluate the number of bits required for storing the final accumulation result of PSD has been presented. Consequently, there is truncation error in the final PSD result, but no overflow or round-off errors. The implemented 35-channel PSD system uses 40 % slices of the Xilinx Viretx-4 SX35 FPGA, along with 70'Xtreme DSP slices'. Tank test results of the EIT instrument fEITER incorporating this digital PSD system have shown good noise performance, achieving an overall SNR of almost80 dB, at the high data-capturing rate of 100 frames/sec. Theresults have also demonstrated the instrument's measurement capability to resolve easily the cases where large conductivity changes occur over very small spatial regions within the subject.

ACKNOWLEDGEMENTSThis work was supported by the Wellcome Trust throughgrant 077724/Z/05/Z. Author STA acknowledges the support of HEC, Govt. of Pakistan for the 10% overseas PhD scholarship, the Wellcome Trust and the Worshipful Company of Scientific Instrument Makers, City of London. Author STA gratefully acknowledges Dr. P. Wright (University of Manchester) for providing the fEITER hardware system he had designed.

ABBREVIATIONS USED

ADC: Analogue-to-digital converter; DFT: Discrete Fourier Transform;DTFT: Discrete-time Fourier Transform; DSP: Digital signal processor;dsp: Digital signal processing;EIT: Electrical impedance tomography;fEITER: Functional Electrical Impedance Tomography ofEvoked Responses;FPGA: Field Programmable Gate Array; MSB: Most significant bitPSD: Phase-sensitive detection; SNR: Signal-to-noise ratio;SQNR: Signal to quantization noise ratio;VHDL: VHSIC Hardware Description Language.

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Title Annotation:Field Programmable Gate Array
Author:Ahsan, S. Talha; McCann, H.
Publication:Science International
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Date:Mar 31, 2014
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