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Cutoff operation of heterojunction bipolar transistors.

Introduction

The gain, efficiency and power of a microwave transistor depend upon the choice of bias point and drive through the familiar designation of operating class (A, AB, B or C). In class A, the transistor is in a conducting state throughout the RF cycle. In the other classes, the device is nonconducting (cutoff) for part of the cycle. Generally, the cutoff classes offer the advantage of higher efficiency but several effects serve to modify the benefits of cutoff class operation. In this paper, a simple model is used to determine the optimum operating class of AlGaAs/GaAs heterojunction bipolar transistors in the absence of clipping [1] and the performance of the device is compared to that of microwave GaAs MESFETs. It is shown that the HBT offers advantages in gain, power and efficiency when used in a microwave amplifier.

Power and Collector Efficiency

A typical HBT amplifier configuration is shown schematically in Figure 1. The voltage and current at the collector can be plotted on the device characteristics as shown in Figure 2. The locus of voltage and current pairs is referred to as the I-V trajectory.

In terms of the current and voltage at the device terminals, the power balance equation for a signal of period [tau] may be written as

[Mathematical expression omitted]

where

[P.sub.L] = the power into the load [I.sub.DC] = the product of the transistor DC currentand voltage [V.sub.DC] = the power input from the DC power supply i(t) = the transistor terminal current V(t) = the transistor terminal voltage

The integral is the power dissipated in the transistor. Since the integral is taken over one period, variables may be changed to radian angle [theta]' and Equation 1 can be rewritten as

[Mathematical Expression Omitted]

First consider the operation in class A. For this case, the transistor is conducting throughout the RF cycle. Let [V.sub.1] be the amplitude of the fundamental frequency component of voltage at the load. If the output tuners present a shunt open circuit at the fundamental frequency and a shunt short circuit at all the harmonics, then [V.sub.1] is the onl voltage component and

[Mathematical Expression Omitted]

where

[Mathematical Expression Omitted]

= the load conductance, as shown in Figure 1

The trajectory of i and V can be superimposed on the transistor I-V contours. The slope of the trajectory is (-gl) and corresponds to the usual class A load line shown in Figure 2. The trajectory is valid as long as [V.sub.1] < [V.sub.DC] -[R.sub.s][i.sub.pk] and [V.sub.1] + [V.sub.DC] < [V.sub.BD] where [R.sub.s] is the transistor saturation resistance defined in Figure 2, [i.sub.pk] is the peak collector current and [V.sub.BD] is the transistor breakdown voltage.

Equations 2 and 3 give the familiar result PL = ([sub.gl.V.sup.2.sub.1]/2. If the base-collector breakdown voltage is sufficienty high, then [V.sub.1] is limited at the top end of the I-V trajectory to [V.sub.DC] -[R.sub.s][i.sub.pk] where [i.sub.pk] = [2.sub.gl][V.sub.1]. Thus,

[Mathematical Expressions Omitted]

and

[Mathematical Expressions Omitted]

Power will be maximum when gl = 1/([2R.sub.s]). The maximum power will be [P.sub.s]/8 where [P.sub.s] = [V.sub.DC.sup.2].([2R.sub.s]). The value of load conductance for maximum power represents a compromise between large voltage swing with a horizontal load line and large current swing with vertical load line.

For power optimized load conductance, the knee voltage, defined as [R.sub.s][i.sub.pk], is [V.sub.DC]/2. The effect of this high knee voltage is to increase the dissipated DC power, lowring the overall efficiency. Using the fact that the DC power is [V.sub.DC][I.sub.DC] = [V.sub.DC][i.sub.pk]/2, it is straightforward to determine that the efficiency at maximum power is only 25 percent. This is one half the value usually quoted as being the maximum efficiency available for class A operation. By choosing a load line for maximum power, a tradeoff has been made with efficiency. The load line for smaller load conductance would intersect the line labeled 1/[R.sub.s] in Figure 2 (the [R.sub.s] line) at a much lower current level. This would give a smaller current swing and lower power, but would reduce the knee voltage and increase the efficiency. The highest efficiency (50 percent) would only be available when the knee voltage (and, therefore, [i.sub.pk] and output power) have been decreased to zero. The need to keep the knee voltage low to achieve high efficiency demonstrates the importance of a low [R.sub.s].

A more general case of Equation 3 is considered in Appendix A. The more general waveform, shown in Figure 3, defines the conduction angle as that portion of the cycle over which the transistor conducts. In Appendix A, expressions for power and collector efficiency are obtained. The case where the current is limited at [theta]'=0 to [i.sub.pk] is considered. The I-V trajectory is limited at the top end by its intersection with the [R.sub.s] line and at its low end at the i=0 axis, as shown in Figure 2.

The results are

[Mathematical Expressions Omitted]

Equations 6 and 7 give important insight into the tradeoff between power and efficinecy of the transistor. Figure 4 shows a set of contours of constant power and constant collector efficiency plotted on the conduction angle and normalized load conductance plane. [P.sub.L] is normalized to [P.sub.s] = [V.sub.DC.sup.2]/([2R.sub.s]) and gl is normalized to 1/[R.sub.s]. For each value of collector efficiency, there is a maximum permitted value of output power occurring at a specific load conductance and a specific conduction angle. Likewise, at each power level there is a maximum efficiency.

The shapes of the power and efficiency contours can be explained. If the transistor is initially biased in class A, the I-V trajectory (with slope [-g.sub.l] is limited at its top end by the intersection with the [R.sub.s] line and at the lower end by the i = 0 axis. The conduction angle can be reduced by decreasing the DC bias current. Harmonic current appears at the output terminals of the device. It may be necessary to increase the RF input power to insure that the I-V trajectory will intersect the [R.sub.s] line.

As the conduction angle is reduced through class AB, the fundamental current is a nearly constant fraction of [i.sub.pk]. This accounts for the horizontal shape of the constant power contours. The efficiency increases as the DC power drops due to the decreasing DC bias current. Therefore, the lines of constant power are intersected by increasingly higher values of efficiency as the conduction angle is decreased.

Continuing reduction of the conduction angle through class C is accompanied by a sharp drop in the ratio between fundamental current and peak current. To keep the output power constant, drive and gl must be increased. This explains the sharp rise in each constant power contour at its critical angle. The associated higher values of [i.sub.pk] increase the knee voltage and decrease the maximum voltage swing. The increased knee voltage results in reduced efficiency. Thus, each constant power curve of Figure 4 below its critical conduction angle intersects curves of decreasing efficiency. The maximum efficiency associated with a given power contour occurs at its critical conduction angle.

The contours of Figure 4 are very helpful in setting operating conditions for optimum power and efficiency. Since the curves are normalized to [P.sub.s], they show the importance of high [V.sub.DC] and low [R.sub.s] for high performance microwave HBTs. The highest powers are in the upper right-hand corner (larger [theta], larger [g.sub.l], while the highest efficiencies are nested in the lower left (small [theta], small gl). The usually stated values of maximum efficiency, that is, 50 percent for class A and 78.5 percent for class B, occur at zero power. For most power levels, the point of maximum efficiency occurs slightly below class B.

Compared with the predictions in Figure 4, higher values of efficiency are possible if the transistor is over-driven to create a clipped current waveform. [1] In this case, the output circuit must present an appropriate match at the harmonic frequencies.

To operate at higher powers with a given efficiency (or equivalently to improve the efficiency without sacrificing power), there are two options, raising the DC bias voltage [V.sub.DC] reducing [R.sub.s]. Raising the DC bias voltage [V.sub.DC] increases [P.sub.s] and provides more power to be traded off against efficiency. But this option is ultimately limited by the collector-base breakdown voltage of the device. Reducing [R.sub.s] reduces the knee voltage ([i.sub.pk][R.sub.s]), decreasing wasted DC power and thus providing more efficiency that could be traded off for more power.

It has been assumed that the turn-on characteristics of the HBT follow an ohmic path with slope 1/[R.sub.s]. The actual characteristics may deviate from this behavior. In particular, there will be an offset voltage of a few tenths of a volt as indicated schematically in Figure 2 and the [R.sub.s] line may bend. Since the only use of [R.sub.s] is at the point of intersection with the I-V trajectory, the described analysis will remain correct as long as the definition [V.sub.knee]/[i.sub.pk] is used for the value of [R.sub.s].

The peak output power density of HBTs is known to be greater than FETs. For field effect transistors, there is a maximum output current that, together with the gate-drain breakdown voltage and the significant leakage current at breakdown, determine an upper limit to the output power of the transistor. The optimum load conductance in class A is usually that which causes the I-V trajectory to intersect the knee at the maximum current and the gatedrain breakdown voltage at zero current.

For a bipolar transistor the limits on the current are not so clear cut. Usually thermal limitations will take effect before theoretical space charge limits such as the Kirk effect become significant. [R.sub.s] of the transistor will also place a limit on the output power for a fixed [V.sub.DC].

For the HBT and the FET, the peak RF voltage amplitude is limited by collector-base and gate-drain voltage, respectively. In cutoff class operation, this limitation becomes more severe for the FET, however. During the off portion of the RF cycle, the gate is driven below the pinchoff voltage. If, for example, the gate-drain breakdown voltage is 20 V and the device pinchoff is -4 V, then even in fully driven class A operation the maximum voltage at the drain can only be 16 V. This limits [V.sub.DC] to somewhat more than 8 V. For class B operation, where the gate drive extends from 0 to -8 V, the drain should be limited to 12 V or slightly more than 6 V for [V.sub.DC]. These effects reduce the power of FETs in cutoff class and FET designers attempt to minimize them by building class B MESFETs with lower pinchoff voltages and higher breakdown voltages as compared with MESFETs designed to operate in class A. HBTs, in contrast, do not suffer this degradation since their higher voltage gain allows the voltage amplitude at the base to remain small compared to the voltage swings at the output terminal.

In FETs, the significant drain leakage currents near gate-drain breakdown reduce drain efficiency. [2] This effect is absent in HBTs that typically show a much sharper collector breakdown characteristic.

Gain and Power-Added Efficiency

Power-added efficiency [eta]A is an important figure of merit in transistor amplifiers, especially in power amplifiers where gain can be low. Power-added efficiency is a function of the gain G given by

[Mathematical Expression Omitted]

HBTs have a power-added efficiency advantage over FETs when operated in cutoff class. A bipolar transistor input current-voltage relationship is nonlinear when the transistor is biased into cutoff. The input circuit behaves like a diode and is nearly cut off over the same portion of RF cycle as the ouput. In contrast, the input circuit of a FET behaves like a series RC circuit. [3] When the FET is pinched off ,the capacitance is reduced but is still not zero. Therefore, the FET input circuit does not cut off as does the input circuit of the HBT.

To illustrate this point, consider two extreme cases of the comparison. For a case with a diode-like input, it is assumed that the input tuning network provides a shunt short circuit at all the harmonics and a shunt open circuit at the fundamental frequency. Then harmonic voltages do not appear and no input power is dissipated at the harmonic frequencies even though harmonic currents are present at the input node. Under this assumption, input and output power are proportional and gain is independent of operating class. Then,

[Mathematical Expression Omitted]

where [G.sub.A] is the class A gain. For gain independent of [theta], the power-added efficiency is easily calculated from Equations 7 and 8.

In an approximation to the situation encountered with the input circuit more like an RC network, the input circuit is conducting throughout the cycle. The amplitude of the input voltage is then [i.sub.A]/[g.sub.m] where [i.sub.A] is defined in Figure 3. In this case, [P.sub.IN] may be written as

[Mathematical Expression Omitted]

where [R.sub.IN] = the effective input resistance [V.sub.g] = the amplitude of the RF voltage at the FET gate [g.sub.m] = FET transconductance From Equations A7 and 10,

[Mathematical Expression Omitted]

and using Equation A9

[Mathematical Expression Omitted]

Equation 12 predicts a 6 dB gain reduction in class B compared with class A gain. [4] The gain change and associated power-added efficiency contours (from Equations 7, 8 and 12) are plotted in Figure 5 for [R.sub.s] = 0. In this case, power-added efficiency peaks in class AB where there is the best tradeoff between drain efficiency and gain. This is in contrast to the earlier case considered with constant gain where the optimum tradeoff was slightly below class B into class C.

Although the two described cases are illustrative of the situation encountered in HBTs and FETs, respectively, they represent extreme cases of gain analysis. In practice, HBT input power dissipation at the harmonics should be taken into account especially in class C when harmonic currents are large. Harmonic power dissipation might result in some gain reduction for the HBT in cutoff class. FETs do have reduced input capacitance when pinched off. Hence, input power dissipation is reduced in cutoff class compared to class A and the gain reduction ameliorated. Nevertheless, one may expect that HBTs have a gain advantage in cutoff class; therefore, they have a power-added efficiency advantage.

Conclusion

The relationship between operating class, power and efficiency has been considered for a heterojunction bipolar transistor in the electronic limit as would apply to short pulse operation. It is found that the HBT saturation resistance and collector-base bias voltage are important parameters in determining the tradeoff between power and efficiency. The analysis applies to large signal operation in the absence of current clipping at the high current end of the I-V trajectory. Advantages of HBTs over FETs for peak power density, gain and power-added efficiency have been suggested.

References

[1] D.M. Snider, "A Theoretical and Experimental Confirmation of the Optimally Loaded and Overdriven RF Power Amplifier," IEEE Trans. on Electron Devices, ED-14, December 12, 1967, pp. 851-857.

[2] S. Wemple, et al., "Relationship Between Power-Added Efficiency and Gate Drain Avalanche in GaAs MESFETs," Electronics Letters, Vol. 16, No. 12, 1980, pp. 459-460.

[3] W.O. Schloser and V. Sokolov, Circuit Aspects of Power GaAs FETs in GaAs FET Principles and Technology, edited by J.V. DiLorenzo and D.D. Khandewal, Artech House, p. 479.

[4] Ibid., p. 509.

Michael G. Adlerstein received his BS degree in mathematics and his MS degree in physics simultaneously in 1966 from the Polytechnic Institute. He received his PhD degree and a second masters in 1971 from Harvard University. During a portion of his doctoral work, he was a visiting scientist at Massachusetts Institute of Technology Francis Bitter National Magnet Laboratory. Since joining Raytheon Company, Research Division in 1971, Adlerstein has worked in the field of microwave and mm-wave semiconductor device research. In 1987, he was appointed consulting scientist. Adlerstein has been associate editor for microwave devices of the IEEE Transactions on Electron Devices (1981-1983) and is publication chairman of the Cornell University High Speed Electron Device Conference Committee. He is a life member of the American Physical Society, Sigma Xi, Sigma Pi Sigma and Pi Mu Epsilon. He is a senior member of the IEEE.

Mark P. Zaitlin received his AB degree in physics from the University of California at Berkeley in 1971 and his PhD in solid-state physics from the University of Illinois at Urbana in 1975. From 1975 to 1977, he did research as a post-doctoral fellow at the Ames Laboratory at Iowa State University. In 1977, he joined the physics faculty at Dartmouth College, where his research activities involved the study of superconducting properties of composite materials. Since 1983, he has been with the Research Division of Raytheon Company, where he has been working in the GaAs semiconductor group. His work has focused on advanced devices and he directed the development of the first 1/4 [micrometer] gate length MBE MESFETs, HEMTs, and pseudomorphic HEMTs. Currently, he is working on fabricating and modeling HBTs for microwave power applications.
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Author:Adlerstein, M.G.; Zaitlin, M.P.
Publication:Microwave Journal
Date:Sep 1, 1991
Words:3000
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