Printer Friendly

Controlling controlled impedance boards: achieving the desired impedence is no simple task.

You are a critical link in the continuous chain of events that must all be successful if your product is to get to market on schedule. If it's a controlled impedance board and it doesn't meet its impedance target spec on the first round, you lose.

If it's a 48-layer, 24 X 48" backplane, each board might cost $50,000. If it's a 26-layer, 24 X 24" load board for a 1,000 pin SOC ASIC, the board might cost you $15,000 each. If it's a 6-layer, 10 X 12" computer motherboard, it might cost you only $20, but every day late may cost $100,000 in lost potential revenue.

How do you minimize your risk and maximize your chance of achieving your target impedance on the first try? The first step is to have a strong working relationship with your lab vendor. You must have confidence in his ability to lab boards to a set of design rules.

The second step is to have confidence in your ability to select the design rules that result in the right target impedance. Enter the most important tool in your tool box, a 2D field solver.

The 2D Field Solver

A 2D field solver is a software tool that solves Maxwell's Equations and calculates the electric and magnetic fields for an arbitrary cross-section transmission line. From these, it also calculates the electrical performance terms, such as characteristic impedance, signal speed, crosstalk and differential impedance. Some field solvers can also calculate the current distributions inside conductors.

FIGURE 1 is an example of the electric and magnetic fields calculated by a common tool. Most 2D field solvers allow changing a geometry term and exploring the impact on an electrical quality such as characteristic impedance. The advantage a 2D field solver wields over an approximation is the flexibility to consider almost any arbitrary cross-section geometry. In addition to the first-order terms such as line width, dielectric thickness and dielectric constant, secondorder terms such as trace thickness, solder mask and trace etch back can be considered.

[FIGURE 1 OMITTED]

FIGURE 2 is an example of the impedance variation as the trace thickness of a microstrip is changed. Here, the impedance drops by about 1.5 [ohm] in going from 0.5 oz. copper to 1 oz. copper. This is a 3% effect.

[FIGURE 2 OMITTED]

Sometimes, knowing that an effect has little impact is just as important as knowing it has high impact, so that it can be ignored to tree up a design constraint and focus attention back on what is really important. A 2D field solver can be your most important weapon in establishing a set of design rules to achieve your target impedance in a robust design.

The characteristic impedance of a transmission line is completely independent of the length of the line. It depends only on the cross-section There are only three geometries where there is an exact, closed form equation that relates the cross-section geometry with the characteristic impedance: a coax, twin cylinders and a single cylinder over a ground plane. These are described in reference 1.

Without exception, the equations offered for every other cross-section are only approximations. While some approximations may be accurate to within a few percent when their assumptions are valid, others can be off by more than 20%, especially for differential impedance. Are you sure you want to take the chance with an approximation when being wrong by 10% could cost you $10,000 to $100,000?

Beware of online calculators. Even though their answers have 3 digits of precision, they are all (unless explicitly stated) based on approximations that cannot be trusted when accuracy is important.

The tolerance on most impedance specs is 10%. High-end systems, especially in test applications, are pushing 5% tolerance. The normal variation in impedance across multiple boards in the same lot is typically 8%. With these levels, why is it important to calculate the impedance with an accuracy better than 5%? It's all about cost. FIGURE 3 shows the distribution in the impedance of product between its control limits.

[FIGURE 3 OMITTED]

If the distribution is centered at the target impedance, you get a high yield. If it is shifted over slightly, the wings of the distribution may be out of spec. To sort these boards will increase the cost of test, and every board out of spec raises the cost of each good board. Centering the distribution by having an accurate set of design rules means the highest yield.

If accuracy is so important, why use a 2D field solver when a 3D field solver must be more accurate? The answer is, it's not. As long as the cross-section is uniform, a 2D field solver can be more accurate than a 3D field solver, will be more than 10 times easier to use and take less than 1/100 of the time to get to an answer. Many of the commercially available 2D field solvers are accurate to better than 1%. See reference 2 for an example.

Front End Design

A 2D field solver is only a tool. it is not a guarantee of a robust design. However, it can play a critical part in the front-end design process and allow you to optimize the stack-up design to balance performance with cost tradeoffs before you go to lab.

The steps in the front-end design process include:

1. Select a target line width. This is based on what your fab vendor can manufacture with high yield, the requirements for routing density, especially near BGA escapes, and the constraints on the conductor losses you can tolerate.

2. Define the cross-section for each layer, whether microstrip, symmetric or asymmetric stripline or broad side coupled stripline.

3. Select the laminate materials and the dielectric constant of the layers based on dielectric loss spec and cost.

4. Using a 2D field solver, calculate the dielectric thickness to achieve your target, either single-ended or differential impedance.

5. Using a 2D field solver, establish the design rule for the minimum adjacent trace spacing to meet your crosstalk spec.

6. Check the total thickness of the board to verify it meets spec.

7. Using a 2D field solver, perform a tolerance analysis and identify the top two or three sources of impedance variation and try to optimize their feature size to minimize their manufacturing variation.

8. Go back to the beginning and optimize the features for manufacturability and cost.

Back End Characterization

No matter how good your design ends up, there are still two important questions no field solver can answer for you: what is the as-fabricated impedance of a specific trace, as a result of manufacturing variations and uncertainty in the dielectric properties of the laminate, and what is the laminate dielectric constant?

The only way to answer these two very important questions is with an instrument to measure the electrical properties of a transmission line. The universally used tool is a time domain reflectometer (TDR). Just as the 2D field solver is the most critical tool for front-end analysis in board design, the TDR is the most critical tool for back-end characterization of board design.

All TDRs work the same way: A precision voltage signal is sent into a transmission line and a sensitive amplifier measures the reflected echo from any impedance changes. In the best case, a TDR will measure nothing, meaning the instantaneous impedance of the board trace is the same as the 50 [ohm] cable connecting to it. A TDR is only sensitive to changes in impedance.

FIGURE 4 shows an example of the measure TDR response from a transmission line with two regions of high and low impedance taken from reference 3.

[FIGURE 4 OMITTED]

Measuring Dielectric Constant

However accurate a field solver may be, it will always be limited by the accuracy with which the dielectric constant of the laminate is known. This has been a major area of contention up and down the supply chain. The fab house is usually caught in the middle trying to communicate between the enduser customer on one end and materials supplier on the other, without really understanding what the customer is asking or how to challenge and push up the learning curve, the materials supplier.

It is not possible to calculate a dielectric constant. It can only be measured, and since it sometimes varies depending on process conditions, it most often must be measured in a fabricated board--either as a test and evaluation board, or in the final product.

The TDR is one of a number of tools that can be used to extract dielectric constant values from a fabricated board. A number of techniques for accurate dielectric constant extraction are outlined in reference 4. They are all based on measuring the time delay of a known length path and from the time delay and length, calculating the speed of the signal.

In a stripline, the dielectric constant is just the square root of the ratio of the speed of light in air, divided by the speed of the signal in the dielectric. Measure the speed of the signal accurately and you get the dielectric constant accurately.

The simplest way of measuring the speed accurately is to use two reference pads to create small impedance discontinuities and measure the round-trip time delay between them (FIGURE 5).

[FIGURE 5 OMITTED]

If these pads are placed on a signal line in a stripline trace, the measured time delay between the pads will provide the speed and from this, the bulk dielectric constant of the laminate.

However, if the signal trace is a microstrip, while the round-trip delay measurement can give the speed, the extracted dielectric constant is the effective dielectric constant, not the bulk laminate value. This effective dielectric constant is not the term that is used in a field solver to calculate the impedance.

The effective dielectric constant depends on the fraction of the field lines that are in the air compared to the bulk value. The only way of extracting the bulk dielectric constant from the effective dielectric constant is with a 2D field solver.

If the stack-up geometry is known, the effective dielectric constant can be calculated based on a value for the bulk dielectric constant. In its simplest form, it's a matter of changing the value of the bulk dielectric constant until the calculated effective dielectric constant matches the measured effective dielectric constant.

FIGURE 6 is an example of this process where the effective dielectric constant was measured for four different microstrips on the same laminate, but with different line widths. We see that the best value of the bulk dielectric constant that matches the measured response is a dielectric constant of 4.1.

[FIGURE 6 OMITTED]

Conclusion

With each board design pushing the envelope of performance, and with the cost pressures every increasing and time to market every shrinking, we have reached the limit to what we can do by working harder. We have to work smarter to achieve our cost, performance and schedule targets.

Two critical tools that should be in every engineer's tool box are a simple-to-use and accurate 2D field solver and a versatile TDR instrument. The combination of these tools can increase your chance of success in your next board design.

REFERENCES

(1.) Bogatin, Eric, "Signal Integrity-Simplified," Prentice Hall, 2003

(2.) See, for example, Online Lecture 130, Stack-up Design with a Field Solver on www.BeTheSignal.com

(3.) OnLine Lecture 624, Characterizing Discontinuities with a TDR on www.BeTheSignal.com

(4.) Online Lecture 623, Accurate PCBTransmission Line Characterization with a 1-PortTDR on www.BeTheSignal.com

DR ERIC BOGATIN is the CTO at IDI, and president of Bogatin Enterprises. Many of his papers are available on his web site, www.BeTheSignal.com. Send e-mail to eric@BeTheSignal.com.
COPYRIGHT 2006 UP Media Group, Inc.
No portion of this article can be reproduced without the express written permission from the copyright holder.
Copyright 2006, Gale Group. All rights reserved. Gale Group is a Thomson Corporation Company.

Article Details
Printer friendly Cite/link Email Feedback
Title Annotation:HIGH-SPEED DESIGN
Author:Bogatin, Eric
Publication:Printed Circuit Design & Manufacture
Date:May 1, 2006
Words:1962
Previous Article:China's evolving RoHs legal regime: the new law goes into effect March 1, 2007 (maybe), and could be even broader than Europe's version.
Next Article:Product development for RoHS and WEEE compliance: environmental compliance regs are here to stay. Learn all about them so you can use them to...


Related Articles
Designing for impedance testing: maintaining signal integrity on impedance-controlled PCBs is easier when the design accounts for the test method....
An alternative PCB architecture for high-speed chip-to-chip signal transmission: copper's 'limits' can be stretched by routing high-speed signals...
An alternative PCB architecture for high-speed chip-to-chip signal transmission: copper's 'limits' can be stretched by routing high-speed signals...
DDR SDRAM characteristic impedance and PCB design: how much impedance variation can a DDR SDRAM interface tolerate before going out of spec?
TDR for differential pair characterization, Part 2: single-ended and differential TDR signatures encompass broad signal integrity applications.
Designing PCBs with mixed materials: mixing the right high-speed, high-frequency materials can improve your board design and keep costs down. But it...
High-speed: PCB design basics: consistency in impedance requires cooperation and coordination between the designer and the fabricator to optimize...
Topology routing tools: speed complex bus system designs: combining the intelligence and skill of an experienced designer with the speed of...
Cost-optimized PCB power integrity design: new analysis tools measure the performance of the power delivery system and consider both cost and...
Designing for high layer count: the design team plays a major role in reducing emissions, increasing immunity and improving signal quality for...

Terms of use | Privacy policy | Copyright © 2021 Farlex, Inc. | Feedback | For webmasters