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Control of high-speed interpolating DACs.

Software-defined radio (SDR) transmission techniques typically involve synthesis of signals at IF or even RF frequencies. To alleviate the problems associated with streaming data at gigahertz rates and further integrate SDR systems, DAC manufacturers offer parts with on-chip clock multipliers, direct digital synthesis (DDS) numerically controlled oscillators (NCOs), interpolating filters, and mixers.

Ideally, by performing the final upconversion digitally on the DAC chip, you only need supply data at the baseband rate. Theoretically, the programmable NCO can bring substantial flexibility to the hardware, allowing spread-spectrum techniques such as frequency hopping to be software controlled.


In phase-sensitive applications such as phased array radar, exact synchronization of multiple DAC outputs is required across multiple trigger events. Separate, fast DACs previously used allowed control of the clock and data inputs, and you could ensure that the clocks and data streams were in sync.

As DAC conversion rates increased beyond 300 MHz, interpolating or digital-upconverter DACs became attractive because they accept data at the baseband rate and perform digital upconversion (DUC) on the chip before generating the analog output. Unfortunately, in most cases, you have limited ability to precisely control the internal DUC functions of these parts.

In one application, an interpolating DAC was operating as a quadrature upconverter that relied on an internal DDS NCO. The phase of any signal generated at the DAC output depended on the phase of the baseband data and the phase of the DDS NCO. Unfortunately, the NCO was free running after the chip was released from the reset condition. Its phase could not be separately controlled. For this application, we needed a register in the chip to control the starting phase of the DDS NCO and an NCO_SYNC pin on the device that would clear the phase accumulator and allow arbitrary synchronization based on an external event.

Interpolation counters and FIR/IIR/CIC filter pipelines also affect the phase of the signal. The state of the interpolation counter determines when new data is accepted into the pipeline. Unless it can be controlled based on external conditions, phase uncertainty exists. And if old, invalid data is not flushed from filter pipelines, it could corrupt the new input.

Because most interpolating DACs do not allow precise external synchronization of important operations in the signal-processing chain, they may not be suitable for phase-sensitive applications. However, there are DUC ASICs available, such as the GrayChip GC4116 and GC5016, that provide this capability (Figure 4).

These devices do require discrete high-speed DACs to do the final digital-to-analog conversion, but these components are readily available. The caveat is that they put responsibility for proper control of the device squarely on the system designer or application programmer. The learning curve may be substantial, but in the hands of an experienced user, these devices are very powerful.

by Scott Hames, Director of Product Management, Interactive Circuits and Systems

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Title Annotation:SIGNAL SOURCES
Author:Hames, Scott
Publication:EE-Evaluation Engineering
Date:Nov 1, 2005
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