# Comparative Simulation Analysis of Process Parameter Variations in 20 nm Triangular FinFET.

1. IntroductionTo continue with the pace of Moore's law, reduction in transistor dimensions causes very significant short channel effects in device. Methods like (i) variable threshold CMOS, (ii) multithreshold CMOS, (iii) transistor stacking, and (iv) power gating are available to reduce the leakage current to some extent but are not suitable for technologies below 22 nm. Fin-FETs are considered as most promising device to reduce SCEs and leakage. FinFET is chosen to replace conventional planar CMOS devices below 22 nm [1, 2]. FinFET is a multigate transistor, in which gate is wrapped around the silicon fin channel. Better electrical control is provided by the wrap-around gate structure and thus leakage current and short channel effects are reduced.

FinFET has several advantages compared to planar devices such as well suppressed short channel effects, reduced subthreshold swing (~70 mV/dec), and small threshold voltage roll-off [3]. Rectangular cross section fins are commonly used for design and analysis of FinFET but they are rarely found in industry. In industries, cross section of FinFET is nonuniform and is similar to trapezoidal shape [4]. In a rectangular or trapezoidal FinFET top fin width can be decreased up to minimum possible value to get triangular FinFET keeping all other parameters the same as those of rectangular or trapezoidal FinFET. Hence, shape of fin is approximately triangle in triangular FinFET.

Triangular fin cross section and 3D schematic representation of triangular FinFET are shown in Figure 1. In this paper, evaluation of on-off current ratio ([I.sub.on]/[I.sub.off]), subthreshold swing (SS), and Drain Induced Barrier Lowering (DIBL) for various process parameters, that is, doping concentration ([N.sub.ch]), oxide thickness ([T.sub.ox]), and fin height ([H.sub.fin]), has been presented for 20 nm triangular FinFET device.

In deep submicron technology, quantum effects become significant. Hence, density gradient model is used in design simulation which incorporates the considerable quantum effects. By considering the quantum effects, more practical environment is provided for device simulation.

This paper has been formulated as follows. Section 2 presents the earlier work on FinFETs. Subsequent section explains the device design and simulation setup. Results have been discussed in Section 4. Conclusion of the workhas been presented in Section 5.

2. Literature Review

In deep submicron technology further downscaling in gate length and oxide thickness can be achieved by varying the device structure of MOSFET. For 10-30 nm channel length double-gate MOSFET (DG-MOSFET) has been considered as most promising device. FinFET process parameters such as [T.sub.ox]. [H.sub.fin], [N.sub.ch], fin width ([W.sub.fin]), and gate length ([L.sub.gate]) highly affect the performance of the device. These process parameters can be varied to achieve the desired performance of the FinFET device such as high on-off current ratio, low DIBL, and low SS. The fin thickness should be kept less than 1/3 of channel length to reduce SCEs [5]. Due to reduction in SCEs and leakage performance is improved in bulk FinFETs compared to planar CMOS. Reduction in fin width leads to decrement in leakage due to SCEs. By optimizing input process parameters for a 22 nm triangular FinFET leakage current can be reduced up to 70% as compared to rectangular fin shape with same base fin width [6]. To overcome the gate oxide leakage current in CMOS devices high-fc gate stack is used. With high-fc gate stack, gate-to channel capacitive coupling can also be improved without any reduction in the gate oxide layer. Variation in work function leads to variation in threshold voltage and it is identified as the main hurdle in scaling of CMOS technology. Below 22 nm technology, due to nonrectangular fin shape, for quantitative estimation of the work-function variation, the work-function values of metallic gate are randomized. Dependence of threshold voltage ([V.sub.th]) on work function can be reduced by 30% for FinFET devices [7]. To characterize Trigate FinFET devices, no complete analytical model is published; in most of the literature, experimental or simulation results are presented. Developing compact model for FinFETs is a very challenging task due to 3D structure and ultrasmall dimensions [3].

Due to presence of the wrapped gate over three sides of semiconductor channel in FinFET devices, the electrostatic control of the gate is improved and several problems of planar transistors are solved. Compact models are one of the important components in circuit simulators which establish a link between the device technology and circuit designers. For different doping concentrations rectangular FinFETs can be accurately modelled [4]. Compared to rectangular fin shape triangular fin cross section reduces the SCEs to a greater extent [2]. The body of bulk FinFET should be lightly doped or undoped, to achieve similar on-state performance in Silicon on Insulator (SOI) and bulk FinFET [8]. In FinFETs, immunity to SCE decreases with increase in [H.sub.fin]. It leads to good subthreshold slope and more significant DIBL. Sidewall angle which can be achieved from a particular process limits the fin height [9].

3. Device Design and Simulation Setup

3.1. Device Design Parameters and Material Composition. FinFET of triangular fin shape with 20 nm channel length is designed on Cogendas GDS2Mesh 3D construction Technology Computer Aided Design (TCAD) tool [10]. The geometrical dimensions used in design are listed in Table 1. Si is used for substrate and fin, and high-fc dielectric Hafnium Oxide is used as gate oxide. Device design is shown in Figure 2.

3.2. Simulation Setup. In this work, triangular FinFET has been simulated at 20 nm gate length for varying [H.sub.fin] and doping using Cogenda's Visual TCAD [11]. In nanoscale devices, quantum effect becomes significant due to very small device size. For such kind of device classical physics model is not suitable for analysis. Hence, quantum physics model is used while simulating the device. The TCAD simulations include density gradient quantum correction model for quantum effects consideration.

An additional quantum potential is included in density gradient (DG) model for calculating the driving force of electrons and holes [10, 11]. The electron and hole quantum correction equation included in simulation is shown as follows [12]:

[mathematical expression not reproducible] (1)

where h is reduced Planck's constant (i.e., h/2[pi]), [m*.sub.n] and [m*.sub.p] are the electron effective mass and hole effective mass, respectively, n and p are the electron concentration in conduction band and hole concentration in valence band, respectively, and q is electron charge.

For Fermi-Dirac statistics, the electron and hole concentration at Ohmic boundaries must be adjusted as per [12]

[mathematical expression not reproducible] (2)

where [K.sub.b] is Boltzmann's constant, T is temperature, [N.sub.c] is effective density of states (DOS) for electrons in conduction band, [N.sub.v] is effective density of states (DOS) for holes in valence band, and [E.sub.F], [E.sub.c,eff], and [E.sub.v,eff] represent fermi level, conduction band edge, and valence band edge, respectively.

Consideration of quantum effects provides more practical environment to design simulation. Net doping profile for fin and active region is shown in Figure 3. Fin height is varied from 10 nm to 40 nm and doping is varied from [10.sup.15]/[cm.sup.3] to [10.sup.18]/[cm.sup.3] for oxide thickness of 1 nm. The impact of doping and fin dimensions like fin height ([H.sub.fin]) on output parameters of FinFET is investigated using TCAD tool. Evaluation of fin height and fin doping concentration corresponding to better device performance is presented.

4. Results and Discussion

Simulation results show that drain current of the triangular FinFET at drain voltage 50 mV decreases with [H.sub.fin] at constant doping concentration of [10.sup.15] /[cm.sup.3] and [10.sup.18] /[cm.sup.3] as shown in Figure 4. Variation of drain current with doping is evaluated for different values of fin height. Drain current decreases with increase in doping level for constant [H.sub.fin] of 15 nm and 40 nm as shown in Figure 5. High channel doping causes more impurity scattering in the crystal and the consequence is that carrier mobility gets reduced, thus resulting in low drain current whereas, in case of low doping concentration, on current is more due to lesser impurity scattering as shown in Figure 5. Drain voltage was kept at 50 mV for measurement of on-off current ratio. On current was studied at gate voltage ([V.sub.g]) = 1V and off current was measured at [V.sub.g] = 0 V.

The variation of on-off current ratio with varying [H.sub.fin] for different doping levels is shown in Figure 6. To maximize this ratio, the doping level should be high (i.e., [10.sup.18] /[cm.sup.3]) because off current is also less in case of high channel doping similar to on current and leads to better on/off current ratio.

Change in gate voltage for a decade change in drain current is known as subthreshold swing (SS). It is calculated using (3) keeping drain voltage at 50 mV.

[mathematical expression not reproducible] (3)

For low doping level, SS reduces with [H.sub.fin]. For high doping levels ([10.sup.17]/[cm.sup.3] and [10.sup.18]/[cm.sup.3]) SS decreases for [H.sub.fin] range of 10 nm to 30 nm and it increases with [H.sub.fin] after 30 nm. Comparison of SS for all the doping levels shows that high doping results in decreased SS as shown in Figure 7.

For DIBL calculations, simulations (at drain voltage 20 mV and 1V) are performed for each combination of input process parameters. The horizontal displacement of the experimental transfer characteristics for [V.sub.d] = 20 mV and 1V at constant drain current is defined as DIBL [13].

The constant drain current at which the horizontal displacement of transfer characteristics is observed for the calculation of DIBL is given as [13]

[mathematical expression not reproducible] (4)

[W.sub.eff] is effective channel width and for rectangular FinFET it is defined as

[W.sub.eff] = 2[H.sub.fin] + [W.sub.fin]. (5)

[W.sub.fin] for rectangular FinFET is constant throughout the fin but for triangular FinFET it varies from [W.sub.fin.bot] to [W.sub.fin.top]. In [14], the equivalent fin width for trapezoidal FinFET with [W.sub.fin,top] = 5 nm and [W.sub.fin,bot] = 15 nm is given at its orthocenter. The same idea can be extended to find the equivalent fin width for the triangular FinFET at its ortho center and can be given as

[mathematical expression not reproducible] (6)

where

[mathematical expression not reproducible] (7)

For the designed triangular device [W.sub.fin,top] = 1 nm, [W.sub.fin,bot] = 15 nm and hence from (7), [alpha] = 1.82353. Since [H.sub.fin] is varied from 10 nm to 40 nm, the value of [W.sub.eff] and [I.sub.DIBL] is listed in Table 2.

DIBL value is improved for high channel doping; this is due to the reason that high doping in the channel lessens the impact of drain potential onto it which further shields channel from drain terminal. In [13], for 25 nm gate length device it is shown that for nonrectangular FinFET device if [W.sub.fin,top]/[W.sub.fin,bot] is less than 0.2 then the range of SS is 74mV/dec to 76mV/dec and DIBL is 80mV/V to 90mV/V. In this work, simulation results show that, with the gate length reduced to 20nm, [W.sub.fin,top] = 1 nm, and [W.sub.fin,bot] =15nm (i.e., [W.sub.fin,top]/[W.sub.fin,bot] = 0.0667), SS can be achieved as low as 65.5 mV/dec and DIBL can be minimized to 32 mV/V as shown in Figures 7 and 8.

On current of device is decreasing with increase in doping concentration; however increasing doping concentration leads to increment in on-off current ratio. SS and DIBL decrease with high doping concentration for 15 nm fin height. Dependence of on current, on-off current ratio, SS, and DIBL on doping concentration for different gate oxide thickness is shown in Figure 9. It is noticed that mobility gets decreased for high doping and thus results in lesser on current and also, leakage current is decreased thus leading to improved on-off current ratio. Better values of SS and DIBL are obtained with doping of [10.sup.18]/[cm.sup.3] as compared to [10.sup.15]/[cm.sup.3]. Oxide thickness of 0.5 nm shows better result for DIBL. This is because of the fact that gate has strong control over three sides of channel for [T.sub.ox] = 0.5 nm compared to that for [T.sub.ox] = 1 nm which reduces the influence of drain over channel. Thus, threshold voltage is less affected by variations in applied drain voltage and results in lower DIBL. Also, the use of Hf[O.sub.2] as gate dielectric can scale the oxide thickness down simultaneously without increasing gate tunneling current.

5. Conclusion

Simulation results show that the variation of process parameters of FinFET has considerable impact on performance parameters of the FinFET. Due to reduced top fin width, gate control over channel is improved and it leads to better performance. On-off current ratio sharply decreases with decrease in doping concentration and increase in fin height. On-off current ratio is improved for high doping ([10.sup.18]/[cm.sup.3]) and minimum fin height (10 nm). SS is better for maximum doping concentration with 20 nm fin height. DIBL is best for maximum doping concentration with 15 nm fin height. For lnm gate oxide, DIBL reduces with doping. For 0.5 nm gate oxide the results are better than that of 1 nm gate oxide provided that fin height is less than 15 nm. For fin height more than 15 nm, performance at 1 nm oxide thickness is better.

Conflicts of Interest

The authors declare that there are no conflicts of interest regarding the publication of this paper.

References

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[7] M. Poljak, V Jovanovic, and T. Suligoj, "SOI vs. Bulk Fin-FET: body doping and corner effects influence on device characteristics," in Proceedings of the 14th IEEE Mediterranean Electrotechnical Conference, pp. 425-430, 2008.

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[11] http://www.cogenda.com/article/Gds2Mesh.

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Satyam Shukla, (1,2) Sandeep Singh Gill, (1) Navneet Kaur, (1) H. S. Jatana, (2) and Varun Nehru (2)

(1) Department of Electronic and Communication Engineering, Guru Nanak Dev Engineering College, Ludhiana 141006, India (2) Semi-Conductor Laboratory, Department of Space, Government of India, Mohali 160071, India

Correspondence should be addressed to Navneet Kaur; navneetkaur@gndec.ac.in

Received 30 July 2016; Revised 31 October 2016; Accepted 17 November 2016; Published 21 March 2017

Academic Editor: Mingxiang Wang

Copyright [c] 2017 Satyam Shukla et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

https://doi.org/10.1155/2017/5947819

Table 1: Geometry of designed FinFET. SN FinFET parameters Value (1) Top fin width (nm) 1 (2) Bottom fin width (nm) 15 (3) Oxide thickness (nm) 1 (4) Fin height (nm) 10 to 40 (5) Doping concentration (/[cm.sup.3]) [10.sup.15] to [10.sup.18] Table 2: Variation of [W.sub.eff] and [I.sub.DIBL] with [H.sub.fin]. SN [H.sub.fin] (nm) [W.sub.eff] (nm) [I.sub.DIBL] ([micro]A) (1) 10 30.042 0.1502083 (2) 15 40.042 0.2002083 (3) 20 50.042 0.2502083 (4) 30 70.042 0.3502083 (5) 40 90.042 0.4502083

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Title Annotation: | Research Article |
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Author: | Shukla, Satyam; Gill, Sandeep Singh; Kaur, Navneet; Jatana, H.S.; Nehru, Varun |

Publication: | Active and Passive Electronic Components |

Article Type: | Report |

Date: | Jan 1, 2017 |

Words: | 2995 |

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