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Comparative Analysis of High Power Density Bidirectional DC-DC Converters for Portable Energy Storage Applications.

I. INTRODUCTION

Recent years have seen a drastic increase in the use of Renewable Energy Sources (RESs) and all types of Electric Vehicles (EVs). A power capacity recorded last year was: solar PV capacity increased by 22 %, constituting 227 GW; wind power capacity increased by 14.5 %, amounting to 433 GW [1]. Also, as compared to 2014, in 2015, electric car stock almost doubled, reaching 1.26 million [2]-[4]. Alternative power sources (compact wind turbines or thin-film solar panels) have become a development trend for portable applications [5]-[11]. Flexible PV blanket mounted on any surface [12], [13] will be quite useful in many applications for charging portable electronic devices.

In general, the technologies described require bidirectional power interface with minimum losses between two DC-busses or a DC-bus and an energy storage device (battery, supercapacitor, etc.). For these purposes, Bidirectional DC-DC Converters (BDCs) should be used. In applications with lower step-up or step-down ratio, a common solution is a non-isolated type [14]--[16]. As compared to isolated converters, it provides high efficiency, high power density, and smaller size and lower cost.

Figure 1 compares non-isolated topologies: interleaved topologies (Fig. 1(a) and Fig. 1(b)) and a cascaded topology (Fig. 1(c)). In those topologies, hard switching control limits their efficiency. Commonly, to overcome that problem and exploit the benefits of Zero-Voltage-Switching (ZVS) or Zero-Current-Switching (ZCS), auxiliary circuitry is used. Resonant switching increases efficiency by reducing switching losses; however, it increases the size, cost, complexity and makes tuning more difficult. Other options are special modulation techniques or increasing the frequency and using the parasitic element of the device as resonant elements (e.g. FETs output capacitance Coss). Still, switching limitation of traditionally used Si MOSFETs lies in the range of couple hundreds of kilohertz, which usually is insufficient.

A solution to this problem can be the use of transistor hetero structures as AlGaN/GaN-based advanced materials. Unique properties of these semiconductors (wide band gap, high values of the charge carrier mobility and saturation velocity, high coefficient of thermal conductivity, etc.) have led to the emergence of devices that have record values of power, voltage and current, as well as the operating frequency (1 MHz-2 MHz) [17]-[20]. High switching frequency allows using extremely small passive elements. At the same time, according to [18], losses in the passive elements are becoming more critical and are limiting the switching frequency.

References [21], [22] illustrate the relations of the switching loss and show some important power losses characteristics. Figure 22 in [21] and Fig. 17 in [22] clearly show that the main contribution in total losses of transistors (especially during ZVS/ZCS switching) are made by conduction losses. Thus, topologies with minimum conduction losses are preferable for further investigations.

This paper provides a comparative analysis of the proposed bidirectional topologies with criteria related to passive volume, voltage stress on semiconductors and conduction losses, to choose a better structure for low-medium power portable applications.

II. CRITERIA FOR COMPARATIVE ANALYSIS OF CONVERTER TOPOLOGIES

This section describes the criteria used for the comparative analysis of the presented topologies.

Evaluation criteria are chosen based on the consideration that the topology should have minimum conduction losses, minimum voltage stress on the semiconductor devices and minimum size of passive components [23]-[30]. The main estimated values here should be represented in relative units (p.u.) to neglect the effect of input/output parameters for final comparison. Also, the analysis is made for one power flow direction (buck operating mode) only at constant output power.

To estimate the contribution of power switches, the value of total voltage stress is taken into consideration as one of the criteria

[T.sub.W] = [[N.sub.T].summation over (i=1)][V.sub.Ti], (1)

where [N.sub.T] is the number of transistors. The amount of power diodes blocking voltage [D.sub.W] is not taken into account because all the presented topologies use synchronous rectifications (diodes connected in parallel with switches), as a result, [T.sub.W] [congruent to] [D.sub.W].

Conduction losses in semiconductors are expressed as

[P.sub.CL] = [[N.sub.T].summation over (i=1)] [I.sup.2.sub.RMSi] x [R.sub.DSoni], (2)

where [I.sub.RMSi] is RMS current through the transistor, [R.sub.DSoni]--drain-source on resistance.

Conduction losses include the sum of power transistors and diodes conduction losses: [P.sub.CL] = [P.sub.TC] + [P.sub.DC]. But due to synchronous rectification, diodes will be conducted only during the dead time between the control signals. This amount of losses can be neglected without a serious impact on the final calculation results. Thus, [P.sub.CL] [congruent to] [P.sub.TC].

Based on our hypothesis, the relative size of inductors and capacitors is proportional to the stored energy, so maximum energy stored in the inductors is

[Vol.sub.L] [congruent to] [E.sub.LW] = [[N.sub.L].summation over (i=1)][[L.sub.i][I.sup.2.sub.AVi]/2, (3)

where [N.sub.L] is the number of inductances in the topology, [I.sub.AV]--average current through the inductor.

Maximum energy stored in the output capacitor

[Vol.sub.C] [congruent to] [E.sub.CW] = [CV.sup.2.sub.AV]/2, (4)

where [V.sub.AV]--average voltage on the capacitor.

III. ANALYSIS OF THE BIDIRECTIONAL CONVERTERS

A. Two-Phase Interleaved Bidirectional DC-DC Converter

The concept of the half-bridge interleaved bidirectional DC-DC converter is proposed and described in [22], [31]-[39]. Figure 2 shows the basic operational modes of an interleaved two-phase converter during the buck state.

Linear-ripple approximated waveforms of inductor currents and output capacitor voltage are shown in Fig. 3. Assuming that the scheme works in the continuous conduction mode (CCM), the dependence between the input DC voltage [V.sub.IN] and the output voltage [V.sub.O] will be

[V.sub.O] = D x [V.sub.IN], (5)

where D is duty cycle.

By means of power balance and assuming an ideal converter (energy conversion efficiency [eta] = 100%), an average output current can be represented as:

[P.sub.IN] [approximately equal to] [P.sub.O] = [V.sub.O] x [I.sub.O], (6)

[I.sub.O] = [P.sub.O]/[V.sub.O], (7)

where [P.sub.IN] and [P.sub.OUT] are input and output power respectively.

Assuming that the topology phases are equally loaded, the output dc current in each inductor will be

[mathematical expression not reproducible]. (8)

Inductor current ripple is represented as

[mathematical expression not reproducible]. (9)

Inductance [L.sub.1] can be represented by well-known formulas [39], but in our case, it is better to express it through the current ripple factor

[mathematical expression not reproducible]. (10)

Thus, inductance is expressed as

[mathematical expression not reproducible]. (11)

A reference condition for calculating relative units for all topologies will be [V.sub.O] = [V.sub.IN]/8. This value is chosen to avoid border conditions and due to schematic limitations of the second topology where the duty cycle D can be only in the range 0 ... 0.5 and the output voltage cannot be higher than [V.sub.IN]/4 [40], [41].

Assume that the condition [V.sub.O] = [V.sub.IN]/8 corresponds to one relative unit of the inductance, thus

[mathematical expression not reproducible]. (12)

Inductance is expressed as

[L.sub.1] = [L.sub.2] = L x [512 x [V.sup.2.sub.O] x ([V.sub.IN] - [V.sub.O])/7 X [V.sup.3.sub.IN]]. (13)

Average voltage on the output capacitor equals [V.sub.O]

[mathematical expression not reproducible]. (14)

Due to a ripple cancellation effect on the interleaved converters, the ripple voltage behavior of the capacitor differs slightly from the conventional buck converter. Rearranging the equations for the capacitor volt-second balance and the capacitor electrical charge [31], [C.sub.O] voltage ripple is evaluated as (Fig. 3)

[mathematical expression not reproducible]. (15)

Output capacitor voltage ripple factor is expressed as

[mathematical expression not reproducible]. (16)

It should be noted that in (15) the coefficient that affects ripple cancellation (1 - 2 x D) x D is correct only for D [less than or equal to] 0.5 . For the value D > 0.5, this coefficient should be (1 - 2 x D') x D, where D'= 1 - D . Thus, the output capacitance value is

[mathematical expression not reproducible]. (17)

For the condition [V.sub.O] = [V.sub.IN]/8, one capacitance relative unit is

[mathematical expression not reproducible]. (18)

Output capacitance is expressed as

[mathematical expression not reproducible]. (19)

Based on Fig. 2, maximum voltage stress on each power switch is

[V.sub.T1..T4] = [V.sub.IN]. (20)

B. Two-Phase Interleaved Bidirectional DC-DC Charge-Pump Converter

Since for the previous topology, general calculation principles are used, for the second topology, equations will be expressed in a similar manner.

Due to the phase switches [T.sub.1] and [T.sub.3] connected in series, it can be clearly seen from Fig. 4 that in the buck mode, the duty cycle of the control signals cannot be equal or greater than 0.5 [40]-[46]. Dependence between the input DC voltage [V.sub.IN] and the output voltage [V.sub.O] will be

[V.sub.O] = [D x [V.sub.IN]]/2. (21)

As in the previous topology (7), assume that current sharing is ideal, so the inductor DC-current is

[mathematical expression not reproducible]. (22)

For further calculations, the value of the voltage on the charge-pump capacitor Ci is needed. It can be expressed from the equation system for inductor volt-second balance [42], [46]:

[mathematical expression not reproducible]. (23)

The obtained capacitor voltage is [mathematical expression not reproducible]. Assuming that the capacitor [C.sub.1] is large enough, the voltage [mathematical expression not reproducible] is considered the same during the whole switching period.

Inductor current ripple is

[mathematical expression not reproducible]. (24)

Current ripple factor for one phase is

[mathematical expression not reproducible]. (25)

Thus, phase inductance can be expressed as

[mathematical expression not reproducible]. (26)

For the condition [V.sub.O] = [V.sub.IN]/8, one inductance relative unit is

[mathematical expression not reproducible]. (27)

The equation for inductance expressed in relative units is

[L.sub.1] = [L.sub.2] = L x [512 X [V.sup.2.sub.O] x ([[V.sub.IN]/2] - [V.sub.O])/3 x [V.sup.3.sub.IN]]. (28)

Based on equations from [40]-[42], the output capacitor voltage ripple is

[mathematical expression not reproducible]. (29)

Taking into account that an average output capacitor voltage should be constant, the voltage ripple factor is

[mathematical expression not reproducible]. (30)

The equation for the output capacitor is expressed as

[mathematical expression not reproducible]. (31)

Based on the condition [V.sub.O] = [V.sub.IN]/8, one relative unit of the capacitance is

[mathematical expression not reproducible]. (32)

Thus, the equation for the output capacitance is

[C.sub.O] = C x (2 - 2 x D) = C x (2 x [8 x [V.sub.O]/[V.sub.IN]]). (33)

From Fig. 4, the total voltage stress on the semiconductors is:

[mathematical expression not reproducible]. (34)

C. Cascaded Bidirectional DC-DC Converter

The most universal solution for a bidirectional power flow interface is a cascaded converter [47]-[59]. This topology can provide either step-up or step-down conversion in both directions.

Control strategies for the cascaded converter can vary. There are some modulation techniques that allow achieving ZVS and thus obtain better efficiency [47]-[49]. To simplify the calculations, a simple buck mode will be used: switch [T.sub.1] acts as the main power switch, [T.sub.2] operates as the main diode, [T.sub.3] is always open [55], [57]-[59]. Figure 5 shows basic operation modes of the cascaded converter.

The relation between the input and the output voltage in CCM is the same as for a conventional buck converter

[V.sub.O] = D x [V.sub.IN]. (35)

Average current in the inductor is

[mathematical expression not reproducible]. (36)

Inductor current ripple is represented as

[mathematical expression not reproducible]. (37)

As for the previous two topologies, inductance is calculated through relative units:

[mathematical expression not reproducible], (38)

[mathematical expression not reproducible], (39)

[mathematical expression not reproducible], (40)

[L.sub.O] = L x [512 x [V.sup.2.sub.O] x ([V.sub.IN] - [V.sub.O])/7 x [V.sup.3.sub.IN]]. (41)

Assuming that the output capacitor voltage ripple changes linearly, the output capacitor in relative units is represented as:

[mathematical expression not reproducible], (42)

[mathematical expression not reproducible], (43)

[mathematical expression not reproducible], (44)

[mathematical expression not reproducible], (45)

[C.sub.O] = C x [8/7] x (1 - D) = C x [8/7] x (1 - [[V.sub.O]/[V.sub.IN]]). (46)

Maximum transistor voltages are:

[mathematical expression not reproducible]. (47)

IV. SUMMARIZED COMPARATIVE ANALYSIS OF THE SELECTED TOPOLOGIES

To sum up the calculation results from Section III, the criteria are used for comparison in all topologies mentioned above. Figure 6 shows the curves for passive elements estimated in relative units, as a function of output voltage. Final formulas are received for the CCM operation mode based on (1)-(4) and placed in Table I. Radar diagrams depicted in Fig. 7 are built at constant output power by using such formulas for three different cases: [V.sub.O] = 0.1 X [V.sub.IN], [V.sub.O] = 0.2 X [V.sub.IN], and [V.sub.O] = 0.4 X [V.sub.IN].

It should be noted that the length of different spokes ([T.sub.W], [P.sub.CL], [E.sub.LW], and [E.sub.CW]) reflects normalized calculated data.

No diagram for an interleaved charge-pump converter is shown in Fig. 7(c) because of the limitations described above.

The comparative analysis showed that the characteristics of conduction losses, the volume of inductive components and the capacitor typical of a cascaded converter are worse than those of other topologies analysed in the paper. As compared to a similar charge-pump topology, the two-phase interleaved bidirectional DC-DC converter has larger total voltage stress on power switches, whereas the conduction losses and the volume of the inductor are similar.

On the other hand, a charge-pump converter has a limitation because its output voltage cannot exceed Vin/4. It restricts the use of such topology in real applications. In the context of further work, the results obtained will be used to choose an appropriate converter topology for low-medium power portable applications.

V. BIDIRECTIONAL DC-DC INTERLEAVED CONVERTER EXPERIMENTAL PROTOTYPE

To verify the proposed comparison method, the models of two converters were analysed in PSIM software. Two-phase interleaved charge pump topology was eliminated due to the limitation on the input to the output voltage relationship. Therefore, models of two-phase interleaved and cascaded topologies were studied in charge and discharge modes with DC-link voltage 12 V and battery voltage 7.2 V. It was concluded that the results observed have a very good correlation with those theoretically received.

Finally, the conventional bidirectional interleaved DC-DC converter was accepted as the best solution. Figure 8 shows the developed 100 W prototype (top view) along with thermal images.

GaN-based transistors GS61008P from GaN Systems were used as a switching device in the experimental prototype. The power source chosen was 2 series connected LiFePO4 18650 cells from A123 Systems with a cutoff voltage from 2 V till 3.6 V and nominal voltage 3.3 V. Prototype parameters are presented in Table II. To reduce conduction losses and decrease overall volume, custom-made inverse coupled inductors were used. The control system is a combination of MCU (STM32F410R8) for data processing and control and CPLD (XC2C256-7VQ100C) for high-frequency PWM generation.

Switching frequency of the two cases was tested: 500 kHz and 800 kHz. Figure 9 shows the voltage and current diagrams across the transistor and the inductor, correspondingly. It should be noted that the voltage spike across the GaN transistors is present. It can be explained by zero deadtime set in the control system in order to minimize conduction losses of GaN transistors.

To estimate total power losses in the converter and prove the right choice of the topology, efficiency was measured by the precision power analyser Yokogawa WT1800 (Fig. 10).

Rough total losses distribution in the converter during maximum load operation is illustrated in Fig. 11. It should be noted that the efficiency analysis does not include losses in the control system, which are about 0.54 W. Conduction losses were calculated using the measured current, the duty cycle and the on-state transistor resistance obtained from the datasheet.

Resistive-based current sensor losses were measured in the same way. Calculation of the switching losses of the transistor was obtained using the numerical values from the transistor datasheet and measured by the oscilloscope Tektronix MSO4043B with passive probes and current probe Tektronix TCP0030A with a bandwidth no less than 100 MHz. Coupled inductor losses were found by subtracting losses of the switches and the current sensor from the total losses. Obtained results were verified with the help of temperature analysis measured by a thermal imaging camera Fluke Ti10. Theoretically, received results show good correlation with those of the thermal analysis.

VI. CONCLUSIONS

This paper proposes comprehensive comparative analysis in order to define the optimal topology for the bidirectional DC-DC converter for low power energy storage applications. Focus in the analysis was concentrated on four parameters: conduction losses, voltage stress, the volume of inductive, and capacitance elements (reflected by maximum energy stored in such components).

Based on proposed approach it is shown that a conventional bidirectional buck-boost interleaved converter can be considered as one of the most suitable solutions. In addition, it was experimentally proven that in combination with modern semiconductor devices, very high efficiency and power density can be achieved.

http://dx.doi.org/10.5755/j01.eie.24.6.22287

Manuscript received 21 May, 2018; accepted 2 October, 2018.

This research is supported by grants (No. 0116U004695 and No. 0116U006960) from the Ukrainian Ministry of Education and Science and has been co-supported by Latvian National Research Program "LATENERGI" and Latvian Council of Science (Grant no. 673/2014).

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Kostiantyn Tytelmaier (1), Janis Zakis (2), Oleksandr Husev (1,3), Oleksandr Veligorskyi (1), Maksym Khomenko (1), Dmitri Vinnikov (3)

(1) Department of Biomedical Radioelectronics Apparatus and Systems, Chernihiv National University of Technology, Shevchenko St. 95, 14027 Chernihiv, Ukraine

(2) Institute of Industrial Electronics and Electrical Engineering, Riga Technical University, Azenes St. 12/1, LV-1048, Riga, Latvia

(3) Department of Electrical Engineering, Tallinn University of Technology, Ehitajate St. 5, 19086 Tallinn, Estonia kostya.tytelmaier@inel.stu.cn.ua

Caption: Fig. 1. Proposed topologies for the comparative analysis: a) two-phase interleaved; b) two-phase interleaved charge-pump; c) cascaded.

Caption: Fig. 2. Two-phase interleaved bidirectional converter in operational mode 1 (a); in mode 2,4 (b); in mode 3 (c).

Caption: Fig. 3. Capacitor voltage and inductor current waveforms of two-phase interleaved topology.

Caption: Fig. 4. Two-phase interleaved bidirectional charge-pump converter in operation mode 1 (a); in mode 2,4 (b); in mode (3).

Caption: Fig. 5. Cascaded bidirectional converter in operation mode 1 (a) and 2 (b).

Caption: Fig. 6. Comparison of passive elements: inductance (a); output capacitance (b).

Caption: Fig. 7. Comparative analysis in terms of weighted criteria at constant output power: for [V.sub.OUT] = 0.1 x [V.sub.IN] (a); for [V.sub.OUT] = 0.2 x [V.sub.IN] (b); for [V.sub.OUT] = 0.4 x [V.sub.IN] (c).

Caption: Fig. 8. Developed 100 W prototype (top view) of the bidirectional interleaved converter (a) and thermal images under full load condition transistors (b), an inductor (c).

Caption: Fig. 9. Voltage waveform across the transistor and current waveform across the inductor.

Caption: Fig. 10. Overall efficiency of the two-phase interleaved bidirectional converter.
TABLE I. SUMMARIZED COMPARISON RESULTS AT CONSTANT OUTPUT POWER.

                                       Topologies

Criteria      Two-phase interleaved         Two-phase interleaved
             bidirectional converter        bidirectional charge-
                   (Fig. 1(a))               pump converter (Fig.
                                                    1(b))

Total            [T.sub.W] = 4 x              [T.sub.W] = 2, 5 x
voltage             [V.sub.IN]                    [V.sub.IN]
stress

Conduction   [mathematical expression      [mathematical expression
losses          not reproducible]             not reproducible]

Maximum      [E.sub.LW] = 2 x L x [64      [E.sub.LW] = 2 x L x [64
energy         x [P.sup.2.sub.O] x           x [P.sup.2.sub.O] x
stored            ([V.sub.IN] -                ([V.sub.IN]/2] -
in the            [V.sub.O])/7 x                [V.sub.O])/3 x
inductors       [V.sup.3.sub.IN]]             [V.sup.3.sub.IN]]

Maximum      [E.sub.CW] = C x [2 x (1      [E.sub.CW] = C x [2 x (1
energy                - 2 x                         - 2 x
stored       [V.sub.O]/[V.sub.IN]) x       [V.sub.O]/[V.sub.IN]]) x
in the          [V.sup.2.sub.O]/3]            [V.sup.2.sub.O]/3]
capacitor

                    Topologies

Criteria      Cascaded bidirectional
              converter (Fig. 1(c))

Total            [T.sub.W] = 2 x
voltage       [V.sub.IN] + [V.sub.O]
stress

Conduction   [mathematical expression
losses          not reproducible]

Maximum      [E.sub.LW] = L x [256 x
energy          [P.sup.2.sub.O] x
stored            ([V.sub.IN] -
in the            [V.sub.O])/7 x
inductors       [V.sup.3.sub.IN]]

Maximum      [E.sub.CW] = C x [4 x (1
energy       - [V.sub.O]/[V.sub.IN]])
stored         x [V.sup.2.sub.O]/7]
in the
capacitor

TABLE II. PARAMETERS OF THE EXPERIMENTAL PROTOTYPE.

Parameter                                         Value

Input voltage, [V.sub.IN]                        4..7.2 V
Output voltage, [V.sub.O]                          12 V
Maximum input current, [I.sub.IN]                  15 A
Maximum output power, [P.sub.Omax]                100 W
Switching frequency, [f.sub.SW]                  500 kHz
Magnetic inductance, [L.sub.S]                    350 nH
Coupling coefficient,                              -0.4
Input/output capacitors, [C.sub.IN]/[C.sub.O]     110 pF
GaN transistors                                  GS61008P
Transistor drivers

Fig. 11. Power losses distribution in the converter at maximum load.

5.83W total losses

Inductor       30%

Transistors,
switching       9%

Transistors,
conduction     42%

Current
sensor         19%

Note: Table made from pie chart.
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Author:Tytelmaier, Kostiantyn; Zakis, Janis; Husev, Oleksandr; Veligorskyi, Oleksandr; Khomenko, Maksym; Vi
Publication:Elektronika ir Elektrotechnika
Article Type:Report
Geographic Code:1USA
Date:Dec 1, 2018
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