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Chipping away the yield: a number of causes add up to the reduced yield and increased cost of CSPs.

Sacrificing cost for real estate, chip-scale packages (CSPs) are projected to reach up to 30% of the market share of all packages sold in only a few years. Currently, CSP assemblies represent 10% of the market; the traditional, larger packages retain a 90% market share. To penetrate the market, the cost of CSPs needs to be closer to that of traditional packages.

CSPs can cost up to eight times more than traditional packages, partly due to the additional processing steps required. Each additional step adds cycle time and subsequent yield loss. After the fab produces a wafer with an acceptable yield, the CSP assembly process faces additional losses in yield: up to 3% in the bump fabrication process; up to 9% during electrical test; and an additional 5% during backend assembly.

What Causes the Yield Loss?

CSP fabrication adds process variation across the wafer and from wafer to wafer. Geometrical tolerancing allows both positional and dimensional variation between bumps. Variation across a wafer and within a die can result in poor electrical contact and yield loss.

The cleaning process can also reduce yield as contaminants on the bumps and hardware effectively increase contact resistance. Contact resistance impedes electrical contact between the device and tester. Optimized cleaning can improve yield and extend the life of test hardware.

Fabrication artifacts and hardware settings both impact electrical test results. Bump location and dimensional variation add instability to the test hardware, while inadequate settings negate an optimized fabrication process. Running design of experiments (DOEs) is a process necessity as poor fabrication processes and hardware settings might contribute to increased contact resistance at the test hardware-to-device interface.

Increased contact resistance will affect test signals and measurement, especially in applications using terminated transmission lines (Figure 1). If the receiver termination ([R.sub.T]) and transmission line impedance (Z) are 50 ohms and the contact resistance ([R.sub.C) is 0 ohms, then the transmission line properly terminates with a load reflection coefficient of ([R.sub.T] - Z) / ([R.sub.T] + Z) = 0. The device would produce [V.sub.O] * [R.sub.T] / ([R.sub.T]+[R.sub.C]) = [V.sub.O] at the tester receiver input.

[FIGURE 1 OMITTED]

The probe contact resistance is near the device output and increases the output source resistance. If the device driver control maintains [V.sub.O] at the output pad, probe contact resistance values of 5 to 50 ohms would cause measured voltage levels to vary 8 to 50% from the true device output. Output current levels would also be lower than expected.

The resulting yield loss might be improved by cleaning the hardware or changing the hardware settings. Cleaning test hardware reduces the contact resistance-to-time zero values, but each cleaning cycle reduces the equipment life. Hardware settings can be changed to improve performance, but damage to the CSPs might result. Both improvements result in increased cycle time during electrical test and might cost the supplier a loss in throughput.

The steps necessary to improve yield at the previous stages may have consequences at backend CSP assembly. Repetitive testing can create deformation on the bumps, and poor hardware settings might damage the bumps. Both induce variation to the CSP assembly process, resulting in yield loss.

What Can be Done?

By summarizing electrical and mechanical defects at various stages of processing and test, an analysis of the results helps identify the three critical areas--CSP fabrication, electrical test and backend assembly--to target for improvement. In-process electrical test has the greatest promise for reducing cost. Yield is lost due to increased impedance during testing at post bump fabrication and CSP assembly. Controlling hardware settings helps manage the variables that contribute to impedance while incurring no capital expenditures and minimal process qualification.

Terence Collier is a

consultant with TQC

Solutions, Dallas, TX;

email: TQCollier@

comcast.net.
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Title Annotation:Guest View; Chip-Scale Packages
Author:Collier, Terence
Publication:Circuits Assembly
Geographic Code:1USA
Date:Nov 1, 2003
Words:633
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