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Charge-trapping devices using multilayered dielectrics for nonvolatile memory applications.

1. Introduction

One of the most attractive candidates for nonvolatile memory applications is the charge-trapping device in which multilayered dielectrics are used. The semiconductor-oxide-nitride-oxide-semiconductor (SONOS) memory is typical of the charge-trapping devices. The advantages of SONOS-type charge-trapping devices include smaller cell size, lower programming voltage, and better cycling endurance compared with the floating-gate devices. By reducing the tunneling oxide thickness in the SONOS-type devices, faster programming speed and lower operating voltage can be accomplished [1-4]. However, the issues of poor retention time and low erase speed still remain in the SONOS-type memory devices. To improve the retention time of SONOS devices, several researches have been reported. Hsu et al. indicated that Hf[O.sub.2] can replace [Si.sub.3][N.sub.4] and obtain a higher conduction band offset for better retention [5]. Reports showed that the retention of memory devices can be improved using a chemical-vapor-deposited blocking oxide [6] or implementing a high-temperature deuterium annealing [7]. Additionally, using a high-k dielectric as the blocking oxide, the program/erase speed and retention characteristic can be improved [8, 9]. In the study using [Si.sub.3][N.sub.4], Hf[O.sub.2], and HfAlO as the charge storage layer, Tan et al. showed that larger band offset can improve the program speed and reduce the overerase phenomenon [10]. Furthermore, using the structures of TaN/Hf[O.sub.2]/[T.sub.2][O.sub.5]/Hf[O.sub.2]/Si (MHTHS) and TaN/[Al.sub.2][O.sub.3]/[Ta.sub.2][O.sub.5]/Hf[O.sub.2]/Si (MATHS) both program speed and retention time can be improved as compared to the traditional SONOS devices [11,12].

In this work, charge-trapping devices using multilayered dielectrics were studied for nonvolatile memory applications. The structure is metal--yttrium oxide--tantalum oxide--silicon oxide--silicon (MYTOS), that is, Al/[Y.sub.2][O.sub.3]/[Ta.sub.2][O.sub.5]/Si[O.sub.2]/Si. The MYTOS devices were fabricated using [Ta.sub.2][O.sub.5] as the charge storage layer and [Y.sub.2][O.sub.3] as the blocking oxide for both high energy barrier at Al/[Y.sub.2][O.sub.3] interface and large dielectric constant. The expected advantages of MYTOS device include longer retention time and faster program/erase speed. Figure 1 shows the energy band diagrams of the MYTOS memory device. The conduction band offset between the tunneling oxide and the high-k charge storage layer is 2.25 eV at the [Ta.sub.2][O.sub.5]/Si[O.sub.2] interface. The large conduction band offset is expected to improve the data retention property because the tunneling electrons can be firmly confined into the charge storage layer. In addition, the [Ta.sub.2][O.sub.5] trap level is about 2.7 eV [13] below the conduction band edge which is much deeper than the 1eV trap level in [Si.sub.3][N.sub.4]. The deeper trap level is expected to further improve data retention characteristic. Aside from the retention property, the SONOS-type devices with high-k blocking dielectrics can increase the electric field for the tunneling oxide at the same operating voltage used. Hence, the program/erase speed can be improved using a high-k blocking layer. In this work, [Y.sub.2][O.sub.3] is chosen to be the blocking oxide in which the charge injection efficiency in the tunneling oxide can be increased; meanwhile, the blocking function can be maintained. The dielectric constant of [Y.sub.2][O.sub.3] blocking oxide is about 15 and the conduction band offset at the [Ta.sub.2][O.sub.5]/[Y.sub.2][O.sub.3] interface is about 1.35 eV. This large conduction band offset is expected to give better blocking efficiency which may improve the memory window characteristic. Besides, this high-k blocking layer is expected to increase the program/erase speed as well as to reduce the program/erase voltage.

2. Experiment

P-type, (100) orientation, and 4-inch diameter silicon wafers with 1-10 [ohm] cm resistivity were used as the starting substrates. A 3 nm tunneling oxide (Si[O.sub.2]) was thermally grown by dry oxidation at 900[degrees]C. The charge storage layer ([Ta.sub.2][O.sub.5]) was deposited by RF magnetron sputtering under a pressure of 1.1 x [10.sup.-3] torr at room temperature in argon gas. The purity of [Ta.sub.2][O.sub.5] target is 99.9%. The thickness of the [Ta.sub.2][O.sub.5] layer is 20 nm. The [Ta.sub.2][O.sub.5] films were either as-deposited or annealed at 400[degrees]C, 500[degrees]C, and 600[degrees]C. The annealing was performed in nitrogen at a flow rate of 3 standard cubic centimeters per minute (sccm). After annealing, the blocking layer [Y.sub.2][O.sub.3] was deposited by RF magnetron sputtering under a pressure of 1.1 x [10.sup.-3] torr at room temperature in argon gas. The thickness of the [Y.sub.2][O.sub.3] blocking layer is 10 nm. For transistor processing, a 500 nm oxide was first grown by wet oxidation and used as the field oxide. The source and drain windows were defined by wet etching and doped by arsenic implantation (5 x [10.sup.15] [cm.sup.-2], 40 keV). The implant was annealed at 950[degrees]C in [N.sub.2] for 30 minutes. The contact region in [Ta.sub.2][O.sub.5] was etched by reactive ion etch (RIE) and in Si[O.sub.2] and [Y.sub.2][O.sub.3] by buffered oxide etch (BOE). The 300 nm thick top aluminum electrodes were evaporated by DC sputtering. Postmetallization annealing (PMA) was performed at 400[degrees]C in [N.sub.2] for 30 seconds. The crystalline phase of the high-k dielectric films was identified by X-ray diffraction (Shimadzu XD-5) using Cu [K.sub.[alpha]] radiation. Separate MHHOS capacitors were also fabricated. The I-V characteristics were measured using Keithley 236 electrometer and the C-V characteristics using high-frequency C-V meter MegaBytek Mi-494.

3. Results and Discussion

Figure 2 shows the [I.sub.ds]-[V.sub.gs] memory window measurement for MYTOS transistors. The [I.sub.ds]-[V.sub.gs] memory window after a 8 V, 0.01 [micro]s program pulse is 1.6 V. The memory window can also be estimated by the capacitance-voltage (C-V) hysteresis curves for the MYTOS capacitors. Using a sweep voltage range of [+ or -] 10 V, the C-V memory window of 1.6 V can be achieved due to the electron trapping (not shown here).

Figure 3 shows the programming characteristics of the MYTOS transistors. Pulse voltages of 6 V or 8 V are first applied to the gate. Thus, the electronscan tunnel from Sisubstrate into [Ta.sub.2][O.sub.5] and be stored into the [Ta.sub.2][O.sub.5] charge storage layer which forms a potential well between Si-substrate and [Y.sub.2][O.sub.3], as shown in Figure 1. In the programevent, [Y.sub.2][O.sub.3] is the blocking layer which can prevent the tunneling electrons from passing across the [Y.sub.2][O.sub.3] layer since the [Y.sub.2][O.sub.3]/[Ta.sub.2][O.sub.5] interface barrier is high enough. Accordingly, the tunneling electrons can be reserved into the [Ta.sub.2][O.sub.5] charge storage layer. The pulse widths are from [10.sup.-8] sto [10.sup.-2] s. After applying the gate pulse, the threshold voltage of the transistor was monitored by measuring the [I.sub.DS]-[V.sub.GS] characteristics. is defined as the gate voltage at 1 [micro]A drain current with [V.sub.DS] = 0.1V. The transistor is defined as "programmed" when the [V.sub.th] shift is larger than 0.5 V. For MYTOS transistors, the [V.sub.th] shift of more than 0.5 V will occur at an applied voltage of 6 V and with a pulse width 10 ns. For MHTHS [11] and MATHS[12], the Vth shift of more than 0.5 V will occur at an applied voltage of 10 V and with pulse widths of 1ms and 100 ns, respectively. Therefore, low program voltage and fast programming speed were achieved with the MYTOS transistors in this work. The MYTOS transistors thus have faster programming speed and lower program voltage than MHTHS and MATHS memory devices. This is most likely due to the larger conduction band offset of 2.25 eV at the [Ta.sub.2][O.sub.5]/Si[O.sub.2] interface compared with 1.2 eV at the [Ta.sub.2][O.sub.5]/Hf[O.sub.2] interface. At the same gate bias where Fowler-Nordheim tunneling is dominating, the electron tunneling distance from Si-substrate to the conduction band of the storage dielectric is therefore shorter for structures with [Ta.sub.2][O.sub.5]/Si[O.sub.2]. The large conduction band offset is expected to give better blocking efficiency which will improve memory window and programming speed. In addition, large conduction band offset can also relieve overerase problem. The program voltage of MYTOS transistor can be as low as 6 V, which is lower than that of 10 V for MHTHS [11] and MATHS [12]. The programming time of 10 ns is also faster than that of 1 ms and 100 ns of MHTHS and MATHS, respectively. As for the erase event, the negative pulse voltage is applied to the Al gate. Hence, the holes can tunnel from Si-substrate into [Ta.sub.2][O.sub.5] and recombine the electrons stored into the [Ta.sub.2][O.sub.5] layer. Figure 4 shows the erase characteristics of the MYTOS transistors. The transistor is defined as "erased" when the reduces more than 0.5 V. Obviously, an applied gate voltage of -6 V is not enough to do the erase process. Meanwhile, the reduced more than 0.5 V at an applied voltage of -8V with a pulse width of 0.1 [micro]s.

Figure 5 shows the retention characteristic of the MYTOS transistors. The [I.sub.DS] versus [V.sub.GS] characteristic was first measured with a sweep voltage from -3 V to 3 V to determine the original threshold voltage. Pulse voltages of [+ or -] 8V at 1 ms duration were then applied for program and erase operations. The threshold voltage shift is measured at different time periods. The MYTOS transistors are projected to have a [DELTA][V.sub.th] window of 0.81V after 10 years. Table 1 lists the comprised memory parameters of the charge-trapping devices in which the adopted trapping layers include [Ta.sub.2][O.sub.5], [Y.sub.2][O.sub.3], Hf[O.sub.2], Zr[O.sub.2], [La.sub.2][O.sub.3], and [Dy.sub.2][O.sub.3] [11-20]. The MYTOS shows faster programming time of 10 ns at a low voltage of 6 V.

4. Conclusion

In summary, Al/[Y.sub.2][O.sub.3]/[Ta.sub.2][O.sub.5]/Si[O.sub.2]/Si field effect transistors were fabricated and investigated. The electrical properties, including memory window, program/erase characteristics, and data retention time, were measured. The [I.sub.ds]-[V.sub.gs] memory window after [+ or -] 8V, 0.01 programming pulse is 1.6 V. The shift of the MYTOS transistors at an applied gate voltage of 6 V with a pulse width of 10 ns is about 1.0 V. As for retention properties, the MYTOS transistors are projected to have a AVth window of 0.81V after 10 years. The excellent performance of the MYTOS transistors is most likely due to the larger conduction band offset at the [Ta.sub.2][O.sub.5]/Si[O.sub.2] and the [Y.sub.2][O.sub.3]/[Ta.sub.2][O.sub.5] interfaces and the large dielectric constant of [Y.sub.2][O.sub.3].

http://dx.doi.org/10.1155/2013/548329

Conflict of Interests

The authors declare that there is no conflict of interests regarding the publication of this paper.

Acknowledgment

The authors would like to thank the National Science Council of the Republic of China, Taiwan, for supporting this work under Contract no. NSC 102-2221-E-130-015-MY2.

References

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Wen-Chieh Shih, (1) Chih-Hao Cheng, (1) Joseph Ya -min Lee, (1) and Fu-Chien Chiu (2)

(1) Department of Electrical Engineering and Institute of Electronics Engineering, National Tsing-Hua University, Hsinchu 300, Taiwan

(2) Department of Electronic Engineering, MingChuan University, Taoyuan 333, Taiwan

Correspondence should be addressed to Fu-Chien Chiu; fcchiu@mail.mcu.edu.tw

Received 6 August 2013; Revised 31 October 2013; Accepted 2 November 2013

Academic Editor: Tung-Ming Pan

TABLE 1: Comprised memory parameters of the charge trapping devices.

Trapping layer    [Ta.sub.2][O.sub.5]    [Ta.sub.2][O.sub.5] [11]
                      (this work)

                         10 ns                  1 [micro]s

Program speed       [V.sub.g] = 6 V          [V.sub.g] = 10 V
                 [DELTA][V.sub.t] = 1V   [DELTA][V.sub.t] = 0.5 V

                        100 ns                    10 ns

Erase speed        [V.sub.g] = -8 V         [V.sub.g] = -10 V
                 [DELTA][V.sub.t] = 1V   [DELTA][V.sub.t] = 0.5 V

Memory window            1.6 V                    0.8 V

Retention               0.81 V                    0.64 V
                  (3 x [10.sup.8] s)        (3 x [10.sup.8] s)

Trapping layer   [Ta.sub.2][O.sub.5] [12]   [Y.sub.2][O.sub.3] [14]

                          10 ns                      0.1 ms

Program speed        [V.sub.g] = 10 V           [V.sub.g] = 8 V
                 [DELTA][V.sub.t] = 0.5 V       [V.sub.d] = 6 V
                                             [DELTA][V.sub.t] = 1V

                        1 [micro]s                10 [micro]s

Erase speed         [V.sub.g] = -10 V           [V.sub.g] = -3 V
                 [DELTA][V.sub.t] = 0.5 V       [V.sub.d] = 8 V
                                            [DELTA][V.sub.t] = 1.5 V

Memory window             2.5 V                      2.3 V

Retention                 0.64 V                      8%CL
                    (3 x [10.sup.8] s)           ([10.sup.4] s)

Trapping layer   [Y.sub.2][O.sub.3] [15]    Hf[O.sub.2] [16]

                          0.1 ms

Program speed        [V.sub.g] = 6 V           1 [micro]s
                     [V.sub.d] = 8 V
                 [DELTA][V.sub.t] = 1.4 V

                       10 [micro]s

Erase speed          [V.sub.g] = -3 V            0.1 ms
                     [V.sub.d] = 8 V
                 [DELTA][V.sub.t] = 2.1 V

Memory window             2.4 V                1.2-1.5 V

Retention                  4%CL                  10%CL
                      ([10.sup.4] s)         ([10.sup.5] s)

Trapping layer       Hf[O.sub.2] [17]          Zr[O.sub.2] [18]

                       10 [micro]s                  0.1 ms

Program speed        [V.sub.g] = 15 V         [V.sub.g]] = 15 V
                     [V.sub.d] = 10 V          [V.sub.d] = 10 V
                  [DELTA][V.sub.t] = 1V     [DELTA][V.sub.t] = 2 V

                          10 [micro]s               10ms

Erase speed         [V.sub.g] = -12 V         [V.sub.g] = -10 V
                     [V.sub.d] = 10 V          [V.sub.d] = 10 V
                 [DELTA][V.sub.t] = 1.5 V   [DELTA][V.sub.t] = 2 V

Memory window             1.5 V                     2.7 V

Retention                  6%CL                      5%CL
                      ([10.sup.4] s)            ([10.sup.4] s)

Trapping layer   [La.sub.2][O.sub.3] [19]   [Dy.sub.2][O.sub.3] [20]

                          0.1 ms                     ~0.1s

Program speed        [V.sub.g] = 9 V            [V.sub.g] = 7 v
                     [V.sub.d] = 9 V        [DELTA][V.sub.t] = 0.5 V
                 [DELTA][V.sub.t] = 2.1 V

                          0.1ms                      ~0.1s

Erase speed          [V.sub.g] = -5 V          [V.sub.g] = -10 V
                     [V.sub.d] = 9 V        [DELTA][V.sub.t] = 0.5 V
                  [DELTA][V.sub.t] = 2 V

Memory window              2 V                       ~1.5 V

Retention                  9%CL                      0.9 V
                          (108s)               (3 x [10.sup.8] s)

CL: charge loss.
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Title Annotation:Research Article
Author:Shih, Wen-Chieh; Cheng, Chih-Hao; Lee, Joseph Ya-min; Chiu, Fu-Chien
Publication:Advances in Materials Science and Engineering
Date:Jan 1, 2013
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