Characterization of a double-doped power HJFET for W-CDMA cellular handset application.
The characterization of handset transmitters is usually dominated by the power devices used. Therefore, selecting the appropriate device is vital for optimum operation. Although a variety of device technologies are available for power application, it has been demonstrated that HJFET is a leading candidate for W-CDMA handset transmitter applications due to its high PAE and low ACPR characteristics.[5-7] The high PAE is achieved by biasing the HJFET with a very low quiescent drain current [I.sub.q] instead of a higher [I.sub.q] (class A operation); W-CDMA ACPR requirements are satisfied under this operation, attributed to an ACPR dip phenomenon.
In this article, an extensive study on the characteristics of a double-doped power HJFET developed for W-CDMA cellular telephones is presented. The optimum device structure is first illustrated with emphasis on achieving low device on resistance [R.sub.on] suitable for low voltage operation. The effects of source and load impedances and quiescent drain current level on the HJFET's performance are detailed, with particular focus on attaining high PAE operation according to the W-CDMA standard. Two distinct ACPR characteristics due to different [I.sub.q] operations are addressed and their dependence on optimum load impedances are discussed. The correlation between ACPRs and third- and fifth-order intermodulation (IM3 and IM5, respectively) distortions are examined. Based on the close correlation, a first-channel ACPR dip phenomenon is explained in terms of a similar IM3 characteristic.
DEVICE STRUCTURE AND DC CHARACTERISTICS
The characteristics of power devices usually dominate the performance of handset transmitters. To achieve the goals of high efficiency under low voltage operation, an optimum device structure with low [R.sub.on] is indispensable.[8,9] Figure 1 shows the optimized structure of the developed double-doped AlGaAs/InGaAs/AlGaAs HJFET. A multilayer cap structure was employed to reduce the [R.sub.on] of the HJFET. A double-recess structure, fabricated by electron cyclotron resonance plasma dry-etching, was adopted to suppress parallel conduction and surface trapping effects, which further reduce [R.sub.on] and prevent premature power saturation. With this optimized structure, the HJFET demonstrates a low [R.sub.on] of 1.4 [ohms]-mm. The active part of the HJFET consists of a 15-nm-thick undoped [In.sub.0.2][Ga.sub.0.8] As channel layer sandwiched between upper and lower Si-doped [Al.sub.0.22][Ga.sub.0.78] As donor layers. A 15-nm-thick undoped [Al.sub.0.22] [Ga.sub.0.78]As Schottky layer was incorporated on the upper Si-doped [Al.sub.0.22] [Ga.sub.0.78]As layer to achieve a high gate-to-drain breakdown voltage [BV.sub.gd]. WSi metal was sputter deposited onto the narrow recess to form a 0.7-[[micro]meter]-long gate.
Figure 2 shows the drain I-V characteristics of the HJFET. The fabricated HJFET exhibited a maximum drain current [I.sub.max] of 580 mA/mm at a gate-to-source voltage [V.sub.gs] of 1.25 V. A maximum transconductance [g.sub.m] of 400 mS/mm was achieved at [V.sub.gs] = 0 V. The [BV.sub.gd] was 14.2 V, measured at a gate current density of 1 mA/mm, and the threshold voltage was -0.6 V.
HJFET POWER PERFORMANCE
Characteristics of power devices such as output power level, linearity and PAE are related to the source and load terminations. In addition, biasing current also plays a critical role in determining device characteristics.[5,6] To obtain the optimum device performance, these parameters must be properly chosen. The effect of these parameters on the W-CDMA performance of the developed HJFET is investigated.
The W-CDMA characteristics of the double-doped HJFET with a gate width of 24.6 mm were evaluated using a QPSK modulated signal with a chip rate of 4.096 Mcps at 1.95 GHz under various [I.sub.q] conditions. The optimum source and load impedances were determined through source/load-pull measurement to obtain a maximum PAE while maintaining an ACPR1 (defined at 5 MHz offset from the carrier frequency with a bandwidth of 4.096 MHz) of less than -43 dBc and an output power Pout of 28 dBm. The measured performance of the HJFET is shown in Figure 3 with an [I.sub.q] of 80 mA (less than one percent of the maximum drain current [I.sub.max]). At a drain bias voltage [V.sub.ds] of 3.5 V, the HJFET exhibited a PAE of 44.2 percent with a [P.sub.out] of 28 dBm and an ACPR1 of -43 dBc. An ACPR1 dip is observed as a function of input power [P.sub.in] at approximately 16 dBm. The dip behavior was determined to be important for the HJFET to achieve high PAE within the W-CDMA criteria.
The characteristic of the same HJFET was also measured under a higher [I.sub.q] level of 300 mA (three percent of [I.sub.max]) with the same source and load conditions. The measured result is shown in Figure 4. The HJFET exhibited a lower PAE of 33.2 percent with Pout and ACPR1 levels similar to the lower [I.sub.q] case. The ACPR1 only increases monotonically with the input power and no dip characteristic is observed.
Figure 5 shows a comparison of the ACPR1 and PAE of the HJFET as functions of Pout for [I.sub.q] = 80 and 300 mA. Both operations achieve the -43 dBc ACPR1 requirement at [P.sub.out] = 28 dBm, but the higher [I.sub.q] operation (300 mA) offers a better ACPR1 for Pout below 26 dBm. It can be seen that the linearity of the HJFET is improved due to the ACPR1 dip phenomenon under the low [I.sub.q] condition at Pout of approximately 28 dBm. As a result of the dip, ACPR1 satisfies the specification resulting in a significant improvement in the PAE over higher [I.sub.q] operation.
The effect of load match on the HJFET PAE and W-CDMA ACPR1 characteristics was also investigated. The measured performance of the HJFET under three different load conditions is shown in Figures 6 and 7 for [I.sub.q] = 80 and 300 mA, respectively. A compromise on the load match between maximum Pout and PAE must be chosen to achieve the highest PAE and optimum ACPR1 at the required Pout level. A similar condition is observed for the higher [I.sub.q] case. It is interesting to note that the ACPR1 dips occur under various cases of load match for the low [I.sub.q] operation, whereas no such dip appears for the higher [I.sub.q] case. The dip characteristic shown here thus can be exploited to improve the PAE of the HJFET while satisfying the ACPR1 specification provided the [I.sub.q] level is appropriately chosen.
CORRELATION BETWEEN W-CDMA ACPRs AND IM DISTORTIONS
Linearity of devices is commonly expressed in terms of either ACPR or intermodulation distortion, depending on the nature of the system (digital or analog). Although ACPR and intermodulation distortion are two different measures, it has been shown that they could be correlated to each other to a certain extent in systems such as North American Digital Cellular and personal digital cellular. Here, the W-CDMA ACPRs of the developed HJFET are compared to its two-tone intermodulation characteristics.
Figure 8 shows the ACPR definition of the W-CDMA system. The first and second adjacent channels are defined at 5 and 10 MHz offset from center frequency, respectively, with a bandwidth of 4.096 MHz. The first and second adjacent-channel ACPRs (ACPR1 and ACPR2, respectively) are defined as the ratio of the main channel power to the first and second adjacent-channel leakage power, respectively. The bandwidths of the IM3 and IM5 distortions are also shown and are estimated based on the bandwidth of the mixing frequencies. Both the IM3 and IM5 distortions fall within the first adjacent channels, whereas only the IM5 distortion is within the second adjacent channel.
The W-CDMA ACPRs of the HJFET were measured with a QPSK-modulated signal having a chip rate of 4.096 Mcps at 1.95 GHz; the intermodulation distortions were measured using a two-tone input signal at frequencies of 1.948 and 1.952 GHz. Figure 9 shows the ACPRs and intermodulation distortions of the HJFET under the low [I.sub.q] operation (80 mA). ACPR1 closely Follows the characteristic of the IM3 distortion with an offset value. The discrepancy at low input power is due to the limited dynamic range of the measurement system. The IM5 distortion is noted to have no obvious correlation with the ACPR1 characteristic, possibly due to its magnitude that is lower than that of the IM3 distortion. It can be clearly seen that the ACPR1 dip arises from a similar characteristic on the IM3 distortion near the same [P.sub.out] level. For the ACPR2, it shows a good correlation to the IM5 distortion.
Figure 10 shows the ACPRs and intermodulation distortions of the HJFET under a higher [I.sub.q] level of 300 mA. Similar to the low [I.sub.q] case, ACPR1 and ACPR2 are correlated to the IM3 and IM5 distortions, respectively. However, ACPR1 is distinctly different compared to the low [I.sub.q] case. The ACPR1 dip does not occur and its level only increases with the output power.
To further illustrate the correlation between W-CDMA ACPR1 and IM3 distortions, the load- and source-pull contours of the HJFET were measured. Figures 11 and 12 show the load- and source-pull ACPR1 and IM3 contours, respectively, plotted on a Smith chart ([Z.sub.0] = 50 [ohms]) for an [I.sub.q] = 300 mA. The input power was equal to 7 dBm in both eases. A good correlation between the ACPR1 and IM3 contours is seen in both figures.
Due to the close correlation, the ACPR1 dip is explained in terms of a similar characteristic on the IM3 distortion. It is understood that the total distortion at IM3 frequency composes distortions generated by odd-order nonlinearities. Assuming the HJFET is weakly nonlinear (which would be valid under normal nonsaturation operation), its characteristic can be represented by up to the fifth-order nonlinearity. The overall distortion at IM3 frequency is therefore the vector sum of the distortions generated by the third- and fifth-order nonlinearities, as shown in Figure 13. When the two distortions have a comparable magnitude and a near out-of-phase difference ([Theta] = 180 [degrees]), cancellation between these distortions would occur, resulting in a dip phenomenon.
A simulation was performed to verify the explanation. An HJFET model was constructed using a large-signal equivalent circuit model, EEHEMT1, available in commercial microwave simulators. The two-tone characteristic was simulated using a harmonic balance technique, and good agreement between the measured and simulated results was observed. Figure 14 shows the simulated effect of third- and fifth-order nonlinearities of the HJFET on the overall IM3 level for the low [I.sub.q] condition (80 mA). The harmonic contents and mixing order used in the simulation were chosen in a way that the two nonlinear effects could be separated. For example, the IM3 distortion generated by fifth-order nonlinearity can be eliminated with a mixing order of less than five. For the case with up to fifth-order nonlinearity, the simulated and measured results show good agreement. However, the IM3 dip does not occur when only the third-order nonlinearity is considered. For an input power below 10 dBm, the third-order nonlinearity dominates the overall IM3 level due to a more linear operation under small signal level.
Figure 15 shows a comparison of the simulated amplitude and phase differences between the two distortions generated by the third- and fifth-order nonlinearities at the IM3 frequency for the low [I.sub.q] operation. At an input power of approximately 16 dBm, the two distortions have a close amplitude response (near 0 dB amplitude difference) and their phase difference [Theta] is nearly 180 [degrees] . These characteristics satisfy the conditions for signal cancellation discussed previously, resulting in the IM3 dip. However, these conditions are only limited to a certain output power level. The ACPR1 dip under the W-CDMA specification also can be explained in a similar manner due to its strong correlation with the IM3 distortion discussed previously.
A double-doped HJFET has been developed to operate at a 3.5 V drain bias voltage for W-CDMA handset applications. The HJFET employs multilayer cap and narrow recess structures, demonstrating a low [R.sub.on] of 1.4 [ohms]-mm that is suitable for low voltage operation. Operating at a low [I.sub.q] of 80 mA, the HJFET exhibited a high PAE of 44.2 percent and an ACPR1 of -43 dBc at an output power of 28 dBm, achieving significant PAE improvement compared to the high [I.sub.q] operation. The high PAE achieved is attributed to the optimum device structure and specific source and load tunings as well as the ACPR1 dip under the low [I.sub.q] condition. The results demonstrate that the developed HJFET is suitable for W-CDMA handset transmitter applications.
The correlation between W-CDMA ACPRs and HFET intermodulation distortions was discussed. It was shown that the W-CDMA ACPR1 and ACPR2 are strongly correlated to IM3 and IM5 distortions, respectively. The origin of the ACPR1 dip phenomenon was determined to be correlated to a similar characteristic on the IM3 distortion. The IM3 dip (and, therefore, the ACPR1 dip) is attributed the cancellation of distortions generated by the third- and fifth-order nonlinearities at the IM3 frequency.
The authors wish to thank M. Kuzuhara, I. Mito and M. Ogawa for their encouragement and support throughout this work.
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Gary Hau received his BEng degree from the City University of Hong Kong, Hong Kong in 1992, and his MSc and PhD degrees from the University of Leeds, UK in 1993 and 1998, respectively, all in electronic engineering. He joined NEC Corp., Japan in 1998. His work involves, research and development of MMIC power amplifiers and other RF components for W-CDMA cellular handsets. Hau's research interests include modeling and analysis of active devices, amplifier linearization techniques and low distortion, high efficiency MMIC power amplifier design.
Takeshi B. Nishimura received his BE and ME degrees in material engineering from Kyoto University and the University of Tokyo in 1991 and 1993 respectively. He joined NEC Corp. in 1993 and has been engaged in the research and development of microwave GaAs devices and MMICs. Nishimura is a member of the Institute of Electronics, Information and Communication Engineers and the Institute of Electrical and Electronics Engineers.
Naotaka Iwata received his BE degree in materials science from the University of Electro-Communications in 1981, and his ME and PhD degrees in materials science from the University of Tsukuba in 1983 and 1999, respectively. He joined NEC Corp. in 1983 where he was engaged in the growth and characterization of III-V compound semiconductors. Since 1989, Iwata has been involved in the research and development of high power FETs using III-V compound semiconductor heterojunctions. He is a member of the Institute of Electronics, Information and Communication Engineers and the Institute of Electrical and Electronics Engineers.
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|Title Annotation:||heterojunction field effect transistor; Technologies for Wireless Applications: Past, Present and Future|
|Comment:||Characterization of a double-doped power HJFET for W-CDMA cellular handset application.(Technologies for Wireless Applications: Past, Present and Future)(heterojunction field effect transistor)|
|Author:||Hau, G.; Nishimura, T.B.; Iwata, N.|
|Date:||Jul 1, 1999|
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