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Challenges extend from simulation to compliance.

High-speed-digital serial I/O links and high-speed memory interfaces continue to evolve--presenting ever-increasing test and measurement challenges. Multilevel modulation schemes, USB 3.1, DDR4/LPDDR4, and MIPI M-PHY are specific areas of focus while issues to be addressed include signal integrity and jitter as well as physical-layer (PHY) characterization, protocol variations, and compliance.

Tami Pippert, Keysight Technologies' high-speed digital marketing program manager, elaborated on one aspect of the challenges. "Modulation schemes are becoming more complex," she said. "Demand for increased network bandwidth in data centers continues to grow. Several industry groups and standards bodies are using or are actively considering multilevel signaling such as pulse amplitude modulation (PAM) since it enables higher data rates for a given channel bandwidth compared to common non-return-to-zero (NRZ) signaling. However, the switch from NRZ to PAM-4 creates many new design and measurement challenges."

Pippert continued, "From a simulation perspective, there is a qualitative change in SerDes toward nontraditional modulation. In the past, SerDes used two-level (NRZ) modulation, but recently there has been a move to introduce novel signaling such as PAM-4." To accommodate this move, she said, Keysight is enhancing its model generation, simulation, and data analysis technologies. "The data analysis is particularly challenging because it is difficult to define bit error rate contour when the eye diagram has three eye openings," she said.

From a test and measurement perspective, she added, PAM-N analysis software for both real-time and sampling oscilloscopes (Figure 1) enables designers to quickly and accurately characterize electrical and optical signals. "Development of new stress types will continue to be required to emulate impairments, and new enabling technologies will evolve," she said. "Modern high-speed arbitrary waveform generators such as the M8195A can provide stressed patterns for PAM-4 and for complex modulation schemes in the future."

Patrick Connally, technical marketing engineer for high bandwidth oscilloscopes at Teledyne LeCroy, agrees on the significance of PAM-4. "PAM-4 poses an interesting test challenge, due to the nature of the four-level PAM-4 signal. The PAM-4 eye diagram comprises three eye openings instead of one and includes 12 types of transitions, whereas NRZ signals have only two. Engineers must understand how their transmitters, channels, and links affect PAM-4 eye quality while quantifying the degree of eye closure due to timing jitter and noise as a function of bit-error ratio (BER)."

Signal integrity is always a key issue for high-speed digital design. Hiroshi Goto, business development manager at Anritsu, commented, "Signal integrity engineers developing high-speed interfaces must validate SerDes, optical transceiver modules, and other PHY devices based on the latest CEI-56G standard supporting 56-Gb/s transfers for electrical interfaces for interconnects being examined by the Optical Internetworking Forum, as well as the 400GbE standard under investigation by IEEE 802.3bs for Internet use supporting transfer of 400 Gb/s. BER, jitter tolerance, and bathtub jitter measurements serve as key indices to assure device design margins and compatible connectivity at these higher speeds."

Chris Nunn, product engineer for modular instruments at National Instruments, cited protocol variations at the application layers as presenting significant test challenges that are difficult to address with fixed functionality instruments. "For example, companies that deploy base stations and small cells into the communication infrastructure around the world commonly use the CPRI protocol as a foundation and then add custom IP and algorithms on top of that foundation," he said. "NI developed its high-speed serial instruments to be software-designed, giving users turnkey functionality for base protocols with the ability to add their own algorithms to the FPGA fabric using NI Lab VIEW--a great advantage of the open and flexible PXI platform."

Nunn said the company recently released the NI MGT (Multi-Gigabit Transceiver) Debug Toolkit for the NI PXIe-6591R/92R high-speed serial instruments (Figure 2). The free software toolkit enables customers to debug and test the PHY of their high-speed serial interface. He said, "This toolkit is a collection of Lab VIEW Vis that allows engineers to dynamically change instrument settings such as line rate, TX emphasis, RX equalization, and the PRBS patterns the card is generating or analyzing." The toolkit also provides BER calculations and link margin analysis through statistical eye scans, he said, adding, "Users also can leverage NI's pre-built examples for out-of-the-box functionality or use the Lab VIEW API to build a custom PHY test solution."

From simulation to compliance

According to Pippert, "Keysight continues to focus on providing and advancing the entire solution for high-speed serial design and test--from simulation to final debug and compliance."

Speaking of simulation, she said, "In the past, the pre-manufacture design could be simulated and tested using compliance tools from an EDA vendor. The post-manufacture prototype could be bench-tested using compliance tools from a test and measurement instrument vendor. However, because of subtle differences between the two vendors' independent approaches to compliance, it was almost impossible to correlate the two." Consequently, the pre-manufacture design might pass and the post-manufacture prototype fail, necessitating a time-consuming and expensive design spin.

To address the simulation-measurement correlation problem, Keysight has introduced the Advanced Design System PCI Express and USB Compliance Test Benches. "By leveraging the same compliance application used on Keysight Infiniium oscilloscopes, the exact same tests are applied to both the premanufacture simulated design and the actual post-manufacture prototype," Pippert said.

For PITY characterization, Pippert said, the Infiniium V-Series oscilloscopes were introduced in February. To help designers find and debug their most challenging problems, the V-Series includes a 12.5-Gb/s hardware serial trigger with a 160-bit sequence. The V-Series also provides 20-GS/s digital channels suitable for triggering, analyzing, and debugging DDR4 and LPDDR4 buses.

In addition, Pippert said, Keysight has expanded the M8000 Series BER test solutions with a 32-Gb/s BERT front end targeted at higher data-rate testing. "The integrated ISI generation allows users to test their receiver over a range of channel losses without the need to manually reconfigure cables on external ISI channel boards," she said. "The analyzer equalization improves measurement accuracy at the higher data rates by 'opening closed eyes' in the looped-back signal from the device under test to the BERT analyzer."

Keysight also offers products addressing interconnect. Pippert said that the N1930B Physical Layer Test System 2015, along with the company's PXI-based VNA with 32 ports up to 26.5 GHz, characterizes high-speed serial interconnect such as cables, PCBs, backplanes, and connectors.

BERT function enhancements

Goto at Anritsu said the company has strengthened the 32G BERT functions of its MP1800A signal quality analyzer (Figure 3) with the introduction of the MP1861A 56/64-Gb/s MUX and MP1862A 56/64-Gb/s DEMUX options. "When used with the MP1800A BERT, the MUX/DEMUX enables generation of NRZ data and BER measurements up to 64.2 Gb/s," he said. "In addition, support for jitter tolerance and bathtub jitter measurements that meet the recommendations of the latest CEI-56G and 400GbE high-speed interface standards is provided."

He added that the MP1861A MUX has a low intrinsic jitter waveform, with random jitter typically measuring 200 fs rms, plus wide output over a broad amplitude range up to 3.5 Vp-p (7 Vp-p differential). In addition, to support high-accuracy measurement of semiconductor characteristics, the MP1862A DEMUX has high input sensitivity of 35 mVp-p (typical, single-ended, eye height).

Chris Loberg, senior technical marketing manager at Tektronix, cited a number of products the company has introduced or updated to support high-speed digital test. The new TekScope Anywhere, he said, is an offline analysis tool that is helpful for conducting correlation from captured oscilloscope data with modeled or simulated waveforms.

In addition, he said, the DPOJET jitter and timing analysis tool received a major update with the addition of noise (amplitude) analysis plus traditional signal timing analysis. "This added dimension is critical for debug of faster digital signal frequencies to determine root cause of closed eyes," he said.

M-PHY, USB 3.1, and DDR4

Specific applications areas Tektronix is addressing include USB 3.1 compliance test automation, MIPI M-PHY compliance testing, and DDR4/LPDDR4 analysis. With regard to this last, Loberg said, "The next big speed bump in memory bus capability is upon us with the DDR4 and LPDDR4 updates from JEDEC. Tektronix has extended its DDR memory bus analysis tools to include support for DDR4 and LPDDR4. In addition, the company recommends use of DDR4-based interposers for more accurate signal capture."

And as for M-PHY, he said, "The MIPI Standards association provides adopters with a family of different PHYs to implement mobile device design buses with. The fastest of these PHYs is M-PHY. With speeds up to nearly 6 Gb/s, M-PHY has important testing needs to validate the high-speed, low-power signaling methods. Tektronix announced an automation package to manage a thorough review of key performance parameters with its DP070000 Series oscilloscope and the AWG7000 arbitrary waveform generator."

In addition, he said, "A very important serial bus interface running at up to 10 Gb/s--USB 3.1 or Superspeed USB--now is on the market. Tektronix introduced a complete transmitter and receiver test solution for this new capability and has provided a test automation suite to measure and report on all of the critical compliance test parameters."

Teledyne LeCroy also is addressing USB and MIPI interfaces. Bob Mart, product manager, said, "The QPHY-USB3.1-Tx-Rx transmit-receive package automates every stage of USB 3.1 transmitter and receiver compliance testing, characterization, and debug. As such, the comprehensive suite performs USB 3.1 testing on both Gen 1 (5-Gb/s) and Gen 2 (10-Gb/s) devices under test according to the latest USB 3.1 specification."

Transmitter testing is performed using the latest SigTest software for official compliance results. Alternatively, Mart said, tests can be run using the SDAIII serial data, noise, and crosstalk analysis option available for a number of Teledyne LeCroy oscilloscopes.

"For receiver testing," he said, "the Protocol-Enabled Receiver and Transmitter Tolerance Tester (PeRT3) fills the gap between PHY test and protocol test. Our new QPHY-USB3.1-Tx-Rx software leverages the QualiPHY automated test framework, which provides connection diagrams, automated oscilloscope operation, and report generation. The PeRT (3) solution performs automated receiver calibration and offers true protocol handshaking support."

He added, "Protocol testing brings to bear the Voyager M310C USB analyzer platform, which offers an integrated USB exerciser option supporting both host and device emulation up to a line speed of 10 Gb/s." In addition, said Mart, "The SPARQ signal-integrity network analyzer makes all time- and frequency-domain measurements required for USB 3.1 cable and connector testing,"

Connally at Teledyne LeCroy commented on the company's QualiPHY MIPIM-PHY automated PHY conformance test software introduced in March. "By measuring a large number of cycles in a short time period, the QPHY-MIPI-MPHY automated PHY conformance test software gives designers a high degree of confidence in new MIPI M-PHY designs," he said. "The QPHY-MIPI-MPHY software performs testing on HS-MODE, PWM-MODE, and SYS-MODE signals at all currently specified GEARs. It is compliant with the MIPI Alliance's Conformance Test Suite for M-PHY 3.0."

Also in March, the company introduced PAM-4 Signal Analysis Software. "The tool makes all essential eye, jitter, and noise measurements on all three eye openings of a PAM-4 signal," Connally said. "This is a requirement for engineers designing next-generation electrical and optical links that seek to double the data-transfer rate by leveraging PAM-4 signaling."

He continued, "The PAM-4 Signal Analysis tool decomposes total jitter and noise in a signal into its random and deterministic components, giving a full accounting of aberrant behavior."

Looking ahead

When asked about trends over the remainder of 2015, Mart at Teledyne LeCroy cited the move to the new, smaller Type C connector for USB. "This connector can transmit different protocols (DisplayPort, MHL, and USB 3.1)," he said, adding, "We have seen more standards shifting toward MIPI support and, in general, a shift toward a mobile-centric posture in the market."

Loberg at Tektronix agreed. "This reversible connector will quickly become a ubiquitous standard for carrying traffic like data (traditional USB up to 10 Gb/s), display (DisplayPort), and power (USB PD) for mobile devices and enterprise computing," he said. "Testing and validating different capabilities through USB Type C will be a hot trend."

Pippert at Keysight also referred to the new connector and related standards efforts, adding, "Validation will require an extensive characterization and compliance regimen."

She also cited "... increased use of DSP at the IC periphery (I/O ring) to mitigate the impairments inherent in low-cost PCB, package, and connector materials. Signal processing algorithms include pre-emphasis, equalization, and clock/data recovery."

Nunn at NI focused on cost of test. "As more lower-cost devices have serial interfaces that must be tested, more affordable instrumentation solutions with sufficient capabilities for testing these devices must emerge," he said. "By using protocol-aware instrumentation, test engineers can quickly and cost-effectively perform functional tests to verify an acceptable SerDes interface. With the addition of user-programmable FPGAs in test instruments gaining favorability, users will be able to further customize their instruments to meet exact application needs such as in-line data processing or closed-loop control."

And finally, Pippert cited the Internet of Things. "IoT will increase the value of connected devices and drive more bandwidth requirements," she said. "The form factor of choice will become QSFP28 PHY copper links with 100 Gigabit Ethernet data rates, and interoperability across devices will continue to drive standardized measurement and compliance approaches."

By Rick Nelson, Executive Editor
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Title Annotation:SPECIAL REPORT: HIGH-SPEED DIGITAL TEST
Author:Nelson, Rick
Publication:EE-Evaluation Engineering
Date:Jul 1, 2015
Words:2217
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