Cadence enhances portfolio of 3D memory verification IP.
INTERNET BUSINESS NEWS-(C)1995-2014 M2 COMMUNICATIONS
Cadence Design Systems, Inc. (NASDAQ: CDNS) said it has announced the availability of verification IP supporting all popular 3D memory standards including Wide I/O 2, Hybrid Memory Cube, High Bandwidth Memory and DDR4 3D Stacking.
The portfolio of memory VIP enables designers to accelerate the verification of memory interfaces and achieve earlier system-on-chip (SoC) verification closure for compute server applications, mobile devices, high-performance graphics and network applications.
Advanced features of these new VIP models include direct memory access for read, write, save, preload and comparison of memory contents, robust assertions, error configurability, transaction callbacks, assertion reports and a built-in address manager. Additionally, the models support all leading third party simulators, verification languages and methodologies, enabling SoC verification teams with the fastest path to verify the correctness of interfaces to these new, specialized memories.
Information about the new products, along with articles and videos pertaining to 3D memory technologies is available at www.cadence.com/news/3dvip.
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. For more, visit www.cadence.com.
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|Publication:||Internet Business News|
|Date:||Oct 24, 2014|
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