Printer Friendly

Cadence and TSMC Develop Foundry-Specific, Timing-Driven Toolkit for SOC Designs; Cooperative Effort Reduces Time-to-Market and Improves Clock Performance.

SAN JOSE, Calif.--(BUSINESS WIRE)--July 5, 1999--

Cadence Design Systems, Inc. (NYSE:CDN) and Taiwan Semiconductor Manufacturing Company (NYSE:TSM) have jointly created a foundry-specific tool kit targeted at high-end system-on-a-chip (SOC) designs.

The new kit features the Cadence(R) system-level-constraint-based, timing-driven design (SLC-TDD) flow, which can reduce design cycle time by up to 300 percent, reduce constraint file sizes by up to 95 percent, and improve clock performance by as much as 25 percent with 100-percent timing coverage.

The SLC-TDD flow, based on Cadence deep-submicron (DSM) tools, achieves single-pass timing convergence in complex, multimillion-gate, deep-submicron designs. The SLC-TDD flow can significantly reduce turn-around time, boost chip performance by 10 to 30 percent, and decrease die size by 5 to 10 percent. To help make the transition, Cadence Methodology Services offers productivity services around the SLC-TDD flow.

"Our relationship with TSMC gives our joint customers access to proven technology, calibrated to their choice of TSMC processes, to solve their time-to-market and design challenges," said Jim Hogan, vice president of IC Implementation marketing at Cadence. "Coupled with the offerings of Cadence Methodology Services, which optimize the flow for customer specific requirements, this relationship presents a winning combination for design teams facing time-to-market and time-to-volume pressures."

"With process geometries headed into very deep submicron territories, it is imperative to more tightly link tools to specific foundry process in order to fulfill the system-on-chip potential that these process technologies offer," said Andley Chang, Design Service marketing, TSMC. "We have already announced the first commercial availability of a true 0.18-micron process. This joint development effort with Cadence is part of our overall strategy to allow designers to quickly ramp to the new process."

Deliverables and Availability

TSMC now offers production-ready 0.35-, 0.25-, and 0.18-micron technology kits targeted for the Cadence SLC-TDD flow. The technology kits consist of technology files, parasitic extraction and physical verification rule files. Included in the rule files is the Assura(TM) HyperExtract parasitic extraction tool, recently benchmarked by TSMC to ensure it met performance criteria.

Since Cadence introduced the SLC-TDD flow in July 1998, Cadence Methodology Services has assisted many customers to facilitate a production-ready flow. These services enable customers to mitigate the schedule and performance risk associated with the technology flow adoption and concentrate on the challenges of bringing their products to market.

About Cadence

Cadence Design Systems, Inc. is the largest supplier of software products, methodology services, and design services used to accelerate and manage the design of semiconductors, computer systems, networking and telecommunications equipment, consumer electronics, and a variety of other electronics-based products. With more than 4,000 employees and 1998 annual sales of $1.2 billion, Cadence is headquartered in San Jose, and has sales offices, design centers, and research facilities located around the world. More information about the company, its products and services may be obtained from the World Wide Web at

About TSMC

TSMC is the world's largest dedicated IC foundry and offers a comprehensive set of IC fabrication processes, including processes to manufacture CMOS logic, mixed-mode, volatile and non-volatile memory and BiCMOS chips. Currently, TSMC operates two six-inch wafer fabs (Fab 1 and 2) and three eight-inch wafer fabs (Fab 3, 4, and 5) all located in Hsin-Chu, Taiwan.

In mid-1998, TSMC announced that production wafers were being delivered from its first U.S. foundry, WaferTech, a joint venture with Altera, Analog Devices and Integrated Silicon Solutions, Inc. The company has broken ground in the new Tainan Park, which will house Fabs 6 and 7, and recently announced its participation in a $1.2 billion joint venture fab with Philips Semiconductor which is scheduled to open in Singapore in 2000. TSMC's corporate headquarters are in Taiwan. More information about TSMC is available through the World Wide Web at

Note to Editors: Cadence and the Cadence logo are registered trademarks, and Assura is a trademark of Cadence Design Systems, Inc. All others are properties of their holders.
COPYRIGHT 1999 Business Wire
No portion of this article can be reproduced without the express written permission from the copyright holder.
Copyright 1999, Gale Group. All rights reserved. Gale Group is a Thomson Corporation Company.

Article Details
Printer friendly Cite/link Email Feedback
Publication:Business Wire
Geographic Code:1USA
Date:Jul 5, 1999
Previous Article:Tri Link Deep Red River Oil Drilling and Production Highly Successful At Tyvan Pool.
Next Article:TSMC Validates Cadence Parasitic Extractor on Processes Down to 0.18 Micron; Cadence Assura HyperExtract Tool Key to Leading-Edge...

Related Articles
TSMC Validates Cadence Parasitic Extractor on Processes Down to 0.18 Micron; Cadence Assura HyperExtract Tool Key to Leading-Edge...
Synopsys and TSMC Introduce First DesignWare Standard Cell Libraries.
Cadence Design Services Announces the SurePath COT Solution; Reduces Risk and Investment Associated with COT Adoption.
TSMC Uses Synopsys Tools for 0.25 Micron Internal Front End Design Flow.
Cadence and TSMC Collaborate to Distribute Design Kits for Baseband and RF Foundry Silicon; TSMC Aligns with EDA Leader to Meet Customers'...
TSMC Adopts Sequence Design Interconnect Modeling Intellectual Property for Technology Characterization.
TSMC Adopts Cadence CeltIC for Signal Integrity Analysis for 0.13-Micron Reference Design Flow.
ARM, Synopsys and TSMC Address Industry Need for Proven SoC Methodologies.
Cadence and TSMC Announce Digital Flow Based On Cadence SoC Encounter; Cadence Platform Validated for Hierarchical SoC Design of 0.18-Micron and...
TSMC 90 nanometer libraries support Nexsys 90NM production.

Terms of use | Privacy policy | Copyright © 2018 Farlex, Inc. | Feedback | For webmasters