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Cadence's Alta Group Introduces First Application-Specific Behavioral Synthesis Solution

Visual Architect(TM) Targets System, ASIC Designers for Wireless and
 Multimedia Product Design

SANTA CLARA, Calif., Design SuperCon97, Jan. 21 /PRNewswire/ -- Cadence Design System, Inc.'s (NYSE: CDN) Alta Group today unveiled Visual Architect(TM), the industry's first application-specific, high-level behavioral synthesis solution. Visual Architect (VA) is the only synthesis offering to provide both system and ASIC designers with a complete and open design flow from high-level algorithm design through optimized silicon.

Visual Architect is the architectural-level entry point of a system-to-silicon design flow for implementing ASICs and FPGAs. Users can leverage VA's integration into Cadence's industry-leading logical, physical, and datapath design solutions; or easily interface it to other commercial or proprietary tools. It provides designers with unprecedented ease of use, full control over ASIC design tradeoffs, and tight integration with EnWave(TM) and EnVision(TM), Alta's application-specific solutions aimed at wireless and multimedia applications, respectively. VA is also the first synthesis solution to solve the dual domain issue (control and datapath) that plagues traditional behavioral synthesis products.

"System design teams for wireless and multimedia products are being challenged to increase integration and keep pace with changing standards while compressing design time," said Alan Naumann, general manager of Cadence's Alta Group. "This first-of-its- kind behavioral synthesis technology, when coupled with implementation tools from Cadence and others, now provides customers with a transparent path from system design through behavioral synthesis, down to floorplanning and place and route. We believe that our current order backlog for Visual Architect is indicative of the customer need for this solution."

Today, a large gap exists between the system-level algorithm expert and the HDL-based ASIC expert in a top-down design flow. The integration of Visual Architect into Cadence's design flow solves this dilemma. System designers capture algorithms in Alta's SPW(TM) that automatically generates behavioral HDL (Verilog or VHDL) for Visual Architect. The system designer then uses Visual Architect to easily generate an RTL architecture for synthesis and to pass that architecture on to the front-end ASIC designer. Finally, the ASIC designer uses Visual Architect to interactively make advanced design trade-offs for an optimal RTL design.

"Alta's new Visual Architect product is an innovative tool that will help us meet tough time-to-market windows and allow us to capture designs at a higher level while compressing our systems-to-silicon design flow," said Frank Eory, principal staff engineer at the Advanced Digital Consumer Division

of Motorola. "As a division that specializes in increasingly complex communications and multimedia ICs, our engineering teams are required to continuously improve our design methodologies and reduce our development cycle times. Using a system-oriented approach to design complex functional blocks, we can reap the benefits of the knowledge base built into the Alta libraries and tools, as well as leverage our own investment and expertise by re-using our existing designs."

Visual Architect

Unlike general purpose logic or RTL synthesis, Visual Architect is an easy-to-use and interactive high-level behavioral synthesis solution that provides full control over architectural decisions within the context of the user's application. Its graphical user interface enables system designers to quickly and easily evaluate synthesis results without requiring an intimate knowledge of HDLs. Visual Architect interactively displays performance and area information based upon architectural decisions.

Visual Architect is based upon technology that was originally developed by Synthesia AB (Stockholm, Sweden) and enhanced through a collaboration with Cadence's Alta Group.

"Cadence's Alta Group has achieved a significant accomplishment with Visual Architect -- a dual domain, behavioral synthesis solution that is open to industry-leading implementation tools," said Gary Smith, senior industry analyst at Dataquest. "These key attributes, along with the application-specific focus, ease of use and full control over ASIC design tradeoffs, will enable Cadence to take a strong offensive position in the market."

"Behavioral synthesis has been around for 10 years, but it's been slow to catch on because it requires a completely different style of HDL coding than at the register-transfer level," said Rita Glover, president and principal analyst at EDA Today in Phoenix, Ariz. "However, Visual Architect enables more intuitive graphical design entry into behavioral synthesis for system-level functional blocks. The result is that this solution offers major advantages for communicating design concepts among the architects of high-performance systems and the engineers who actually design the chips, especially in the communications and multimedia fields."

Pricing and Availability

Available now on Sun and Hewlett-Packard UNIX machines, Visual Architect is priced at $70,000.

Cadence's Alta Group is the leading supplier of system-level development solutions (tools, libraries, and services) that are focused on the early, high-level portion of the design cycle where fundamental design decisions are made.

Cadence Design Systems, Inc. provides comprehensive services and technology for the product development requirements of the world's leading electronics companies. Cadence is the largest supplier of software tools and professional services used to accelerate and manage the design of semiconductors, computer systems, networking and telecommunications equipment, consumer electronics and a variety of other electronic-based products. With more than 3,000 employees and annual sales in excess of a half-billion dollars, Cadence has sales offices and research facilities around the world. The company is headquartered in San Jose, Calif., and is traded on the New York Stock Exchange under the symbol CDN.

NOTE: Visual Architect, EnWave, EnVision, SPW and HDS are trademarks of Alta Group of Cadence Design Systems. Cadence Design Systems Inc. and Alta Group are registered trademarks of Cadence Design Systems, Inc.

SOURCE Cadence Design System Inc.
 -0- 01/21/97

/CONTACT: Melissa Baten Caswell for Alta Group of Cadence Design Systems, 408-523-4101, or; or Diane Orr of Tsantes & Associates Inc., 408-452-8700, or, for Cadence Design Systems/


CO: Cadence Design System Inc. ST: California IN: CPR SU: PDT

GZ-TW -- SFTU037 -- 0903 01/21/97 13:01 EST
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Date:Jan 21, 1997
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