CRAY RESEARCH REVEALS KEY FEATURES OF FIRST MPP SYSTEM
CRAY RESEARCH REVEALS KEY FEATURES OF FIRST MPP SYSTEM "True Supercomputer Technology" To Alleviate Performance Bottlenecks In Current MPP Products EAGAN, Minn., Oct. 26 /PRNewswire/ -- World supercomputer-leader Cray Research, Inc. (NYSE: CYR) today disclosed key technical features of the company's first massively parallel processing (MPP) system due out in 1993.
Company officials said that by using true supercomputer technology, Cray Research's MPP system will alleviate major performance bottlenecks found in current MPP products and will be "the world's first multi-purpose MPP system useful for real production work."
"MPP has enormous potential for tackling highly parallel programs, but current MPP products have notable deficiencies," said Cray Research vice president of technology Steve Nelson. "It's not enough to employ large numbers of fast microprocessors; what's needed is a balanced system that matches fast processor speed with fast I/O (input/output), fast memory access and capable software," he said. Cray Research is applying 20 years of experience with balanced, efficient parallel vector supercomputers to address current MPP deficiencies." As evidence of current MPP deficiencies, company officials cited recent studies done at leading national laboratories, in which Cray Research's parallel vector supercomputer systems outperformed current MPP products even on highly parallel programs: -- In a recent NASA Ames Research Center study(1), the CRAY Y-MP C90 system outperformed current MPP systems on a series of parallel problems, including one termed "embarrassingly parallel." "The 16- processor CRAY C90 system is consistently the highest performing system tested, far surpassing any of the highly parallel systems," the study concluded, adding that "the performance rates on the highly parallel systems are typically only two to five percent of the theoretical peak performance of these systems," versus "more than 50 percent in some cases" for the C90 system. "The results show that on these codes, only the Cray currently demonstrates gigaflops (more than a billion floating point operations per second) performance," said Dartmouth College's Dr. George Cybenko and the University of Illinois' Dr. David J. Kuck in a Sept. 1992 article in IEEE Spectrum. -- Another study(2) at Los Alamos National Laboratory concluded: "In our tests, the massively parallel machine is faster |than the CRAY Y-MP8 system~ on none of our full applications when the fully configured systems are compared." The NASA Ames and Los Alamos studies identified the same major performance bottlenecks of the current MPP systems: immature software compilers, inadequate memory bandwidth, and insufficient bandwidth between the individual processors. Both studies are slated for presentation at the IEEE Supercomputing '92 conference in November. "What the world needs now is an MPP system built with true supercomputer technology," said Nelson, "and Cray Research intends to be the first to deliver it." He said today's RISC microprocessors lack the communication, memory and synchronization features needed for efficient MPP systems. "Cray Research plans to circumvent these shortcomings by surrounding the RISC chips with powerful communications hardware. Cray Research's state-of-the-art IC (integrated circuit) fabrication facility allows us to design and produce the high-performance switch hardware in a relatively short timeframe. Our MPP system will also exploit our supercomputer packaging and cooling techniques," he said. "In this way, we plan to transform thousands of commodity RISC processors into a supercomputer-class MPP system that can address terabytes of memory, minimize communication overhead, and provide flexible, lightweight synchronization. Programs running on our MPP system will operate in a normal UNIX environment." Nelson disclosed additional key features of the company's first MPP system, code-named T3D, that is scheduled for 1993 availability: Heterogeneous Architecture For Real Workloads "MPP systems are designed to run highly parallel problems, but supercomputing production workloads include a mix of scalar, vector, parallel and highly parallel software codes," Nelson said. "To maximize production throughput, Cray Research will closely couple its MPP system with the industry-leading parallel-vector-scalar architecture of the CRAY Y-MP supercomputer line, including the CRAY Y-MP C90 and large- memory CRAY Y-MP M90 systems." Nelson said customers will be able to purchase either complementary MPP capabilities for their existing CRAY Y-MP supercomputer systems, or single-chassis systems containing closely coupled MPP and Y-MP capabilities. A wide variety of system configurations will be available, featuring different mixes of MPP and parallel-vector-scalar capability to meet specific customer needs. Cray Research's UNICOS operating system will provide a coherent environment for distributing programs across both architectures. "This total computational capability simply does not exist on any MPP or clustered workstation system in the market today," he said. MPP Emulator To help customers develop programs for Cray Research's MPP system before its 1993 arrival, Nelson said, the company has developed an MPP emulator that allows users to run MPP applications on their CRAY Y-MP systems. The MPP emulator helps developers write more efficient parallel code, by providing feedback on data layout, data locality, and data reference patterns. MPP Macroarchitecture "The heart of Cray's first MPP system is a balanced, scalable macroarchitecture that combines powerful Alpha microprocessors from Digital Equipment through a high-bandwidth, low-latency interconnect network that will be an order-of-magnitude faster than those of current MPP systems," said Nelson. He described specific features of the macroarchitecture: -- A MIMD (multiple-instruction, multiple-data) architecture that can also efficiently emulate SIMD (single-instruction, multiple data) and multicomputer MIMD architectures. -- A high-speed interprocessor communications network will link the processing elements (PEs) to distribute and access global data. The network uses the same high-performance switch technology as the CRAY Y- MP processor/memory interface and operates at the same 150-Mhz clock speed as the PEs to provide extremely fast non-local access. -- 3-D torus interconnect topology. A key feature of Cray's MPP system is a three-dimensional interconnect network that increases bandwidth and minimizes network distances. The 3-D torus gives Cray Research's MPP system the highest bisection bandwidth of any known MPP. Its shape keeps the nodes close to each other, avoiding the "far neighbor" communication delays found in other MPP systems. The T3D uses high-performance switch nodes that handle interprocessor communications without interrupting the PEs. Each switch node can operate bi- directionally in each dimension. -- A globally addressable, physically distributed memory. Because the memory is logically shared, any PE can access the memory of any other processing element without explicit message passing, and without involving the remote PE. As a result, the system can be scaled to address terabytes of memory. This design provides ease-of-use, high memory bandwidth and low memory latency. -- Latency hiding. To help sustain high performance, special communication hardware will allow data in remote PEs to be moved to a local PE before it is needed. -- Fast synchronization -- a rich set of synchronization primitives for both MIMD and SIMD programming. -- High-bandwidth, parallel I/O. Cray's MPP system will connect to the company's industry-leading I/O subsystems with multiple high-speed channels. -- Microkernel-based operating system. Each PE will have a microkernel that manages communications with other PEs and with the closely coupled CRAY Y-MP vector processors. -- Scalability. The interconnect design will allow customers to scale easily from tens to hundreds to thousands of PEs. -- Easy porting to future systems. To protect customer software investments, programs written for Cray's first MPP system will port easily to future Cray MPP systems. -- Reliability (fault-tolerance). Software-configurable redundant hardware will be included so that processing can continue, without hardware maintenance, should a PE fail. MPP Microarchitecture As previously announced, our first MPP system's microarchitecture will be based on Digital Equipment's Alpha processor, which has scalar performance of 150 megaflops and supports IEEE standard 64-bit floating- point and logical arithmetic. We will use it in industry-standard Big Endian mode," Nelson said. "For our future MPP systems, we will use the fastest microprocessors available at those points in time." Application Software Focus "Cray Research's MPP system will be a powerful platform not only for those applications that are fairly well understood in the MPP arena, but also for key applications, such as CFD and crash analysis, that have not been practical on other MPP systems," Nelson said. Nelson said Cray Research's MPP system is designed to allow customers' existing MPP codes to be ported easily, typically with improved performance. The system will support message-passing, data- parallel and MPP Fortran programming models. MPP Fortran is a precursor to High-Performance Fortran (HPF). Cray Research has been actively involved in the effort to develop HPF. Cray Research will focus application software conversion on key MPP application areas: -- Seismic data processing for petroleum exploration -- Atmospheric modeling for weather prediction/climate research. -- Computational fluid dynamics (CFD) and structural analysis for the aerospace and automotive industries. -- Computational chemistry for drug design and materials science applications -- Computational electromagnetics Nelson said Cray Research has worked closely with an MPP advisory group consisting of leading-edge government, university and commercial customers who have had experience with current MPP products. "This direct input has been invaluable in telling us what works and what doesn't work in the MPP arena, from the customers' standpoint." He repeated the company's previously announced three-phase MPP program. Plans call for delivering the first-phase MPP system in 1993, with 150 gigaflops peak performance in a 1024-processor configuration, scalable to 300 peak gigaflops in a 2048-processor version; the second- phase system in mid-decade, with peak performance of a teraflops (trillion floating point operations per second); and the third-phase system in 1997, with sustained teraflops performance. As previously announced, DARPA, the Defense Advanced Research Projects Agency of the U.S. government, is investing $12.7 million in funding support for the first three years of Cray Research's MPP program. "Cray Research's strategy for providing a massively parallel computer system will result in a solid, well-balanced product," said W.R. Rhodes, Special Project Manager, Mobil Exploration and Producing Technical Center in Dallas. "From what I've seen in technical presentations, our people won't have to spend a lot of time worrying about hardware stability. The biggest challenge with MPP today is the software environment and availability. Cray has traditionally viewed software as very important and they have maintained substantial resources to address this component." Wolfgang Nagel, director of Parallel Computing for Forschungszentrum Juelich (KFA), Juelich, Germany, said, "The CRAY T3D programming model provides an extremely flexible and user-friendly MIMD-oriented concept, and it will certainly be a most promising feature of the Cray MPP system." He added that "the network of Cray's T3D system is certainly a significant step into powerful communication technology strongly required to hit the target of teraflops." Cray Research creates the most powerful, highest-quality computational tools for solving the world's most challenging scientific and industrial problems. (1) David H. Bailey et al., "NAS Parallel Benchmark Results," NASA Ames Research Center. Paper to be presented at IEEE Supercomputing '92 conference, Nov. 1992. (2) Margaret L. Simmons et al., "The Performance Realities of Massively Parallel Processors: A Case Study," Los Alamos National Laboratory. Paper to be presented at IEEE Supercomputing '92 conference, Nov. 1992. -0- 10/26/92 /CONTACT: (Media) Steve Conway, 612-683-7133 or (Financial) Bill Gacki, 612-683-7372/ (CYR) CO: Cray Research, Inc. ST: Minnesota IN: CPR SU: PDT
KH -- MN002 -- 4519 10/26/92 07:35 EST
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|Date:||Oct 26, 1992|
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