CEVA'S NEW DSP CORE DELIVERS HIGHEST AUDIO PERFORMANCE.
The new CEVA-TL3211 DSP core is compliant and code compatible with the CEVA-TeakLite-III architecture, which was recently named the industry 'best all around audio processor' in an independent report(1). The CEVA-TL3211 is a 32-bit audio DSP running at 1GHz with a silicon footprint of only 0.2mm^2 when implemented on a 40nm process node. Specifically benefitting the DTV and STB markets, the CEVA-TL3211 runs a complete DTV use-case in less than 200MHz, leaving ample headroom for vendors to run various post-processing functions on the same core, thereby reducing overall cost. For low cost smartphones, the CEVA-TL3211 allows an efficient integration of baseband processing along with application processing related needs like HD audio and voice enhancements such as noise cancellation and beam forming.
"Next generation audio processing solutions must meet a broad set of demanding requirements, including performance, multi-stream codec support and stringent cost targets. In a recent study, we found the CEVA-TeakLite-III architecture the best all around processor for audio applications based on those criteria. The enhancements CEVA has made with the CEVA-TL3211 make it even better positioned for implementing HD audio functionality in a wide range of products," said Joseph Byrne, Senior Analyst, at The Linley Group.
The CEVA-TL3211 DSP core is fully backwards compatible with earlier members of the CEVA-TeakLite family, including the CEVA-TL3210 DSP core, CEVA-Teak, CEVA-TeakLite, and CEVA-TeakLite-II DSPs, allowing licensees of these earlier DSP cores to easily reuse their existing code. The CEVA-TL3211 further reduces development time through its fully cached memory subsystem and CEVA's production-proven application optimizer and software development environment. On top of its industry-leading performance enabling simultaneous multi-codec and multi-stream processing, the flexible CEVA-TL3211 DSP core offers:
Full support for the latest HD audio codecs required for premium quality sound. These include the Dolby MS10 and MS11 Multistream codecs for next generation DTV and STB designs, as well as the complete DTS-HD audio codecs.
A flexible fully cached design (program and data), including L2 cache support, that allows rapid algorithm development and supports the use of real-life system DDR constraints, contributing to lower cost of the end product; CEVA's innovative Power Scaling Unit (PSU) supporting clock and voltage scaling, reducing power consumption, lowering heat dissipation, and allowing cheaper IC packaging;
Full duplex AXI buses for lower power, higher performance and easier integration into modern SoCs; A robust software development environment to ease software migration and facilitate C-level programming
"The new CEVA-TL3211 extends the most popular and extensively deployed DSP architecture, with more than 100 design wins, 1.5 billion devices shipped to-date and more than 90 fully optimized audio and voice codecs. We have leveraged our production-proven CEVA-TeakLite-III DSP architecture for the specific needs of next-generation audio and voice applications, such as DTVs, STBs and smartphones, providing the industry's most powerful audio and voice processor available to-date," said Eran Briman, vice president of marketing at CEVA. "We have a track record of working with leaders in audio technology, and our innovative features such as the solution's power scaling unit, its efficient memory utilization and its substantial audio processing capabilities allow product designers to meet their market requirements faster and with lower risk."
Meeting Demanding HD Audio Requirements
The CEVA-TL3211 DSP core features native 32-bit processing, including a single-cycle 32x32-bit multiplier, a 32-bit register file, 64-bit wide memory bandwidth, 72-bit accumulation for wide dynamic range, as well as efficient bit-manipulation capabilities. In addition to supporting up to three instructions running in parallel, the CEVA-TL3211 also supports single-precision and double-precision FFT instructions for efficient codec implementations. These features clearly distinguish the CEVA processor from other IP vendors, and deliver full 32-bit precision for the most efficient implementation of HD audio standards.
The CEVA-TL3211 includes an innovative memory subsystem, supporting the use of program cache memory, 2-way set associative data cache memory, configurable cache and TCM sizes, and user selectable write policy. The cached memory subsystem further supports automatic pre-fetch for increased efficiency, the use of a level 2 system cache, and non-blocking transactions. The CEVA-TL3211 memory subsystem allows CEVA to optimize HD Audio codecs utilizing smallest on-chip memory, and excellent system DDR robustness.
CEVA-HD-Audio Solution Incorporates Broad Codec Support
The CEVA-TL3211 DSP core is coupled with a set of optimized audio and voice codecs, available as part of the CEVA-HD-Audio solution. Occupying only 0.2mm^2 in 40nm process node, this single-core solution is the most compact and power-efficient HD audio offering available for integration into home entertainment and consumer ICs, with lower overall cost and reduced die size compared to other audio solutions, some requiring dual processors for advanced audio use-cases such as Blu-ray Disc.
In addition to a host of mainstream codecs like MP3, AAC, HE-AAC, WMA, WMA Pro, and RealAudio, the CEVA-TeakLite-III architecture is supported by a suite of fully-certified HD-Audio codecs that are available directly from CEVA. These include Dolby codecs (Dolby Digital, Dolby Digital 5.1 encoder, Dolby Digital Plus, Dolby TrueHD, Dolby ProLogic IIx) and DTS codecs (DTS core decoder, DTS 5.1 encoder, DTS-HD LBR, DTS-HD Master Audio, DTS NEO:6). All of these codecs are optimized for minimal internal memory usage and are tailored to reduce overall system speed requirements and external memory bandwidth.
The CEVA-TeakLite-III architecture also supports a wide range of voice codecs and telephony functions, including G.7xx, narrow and wide-band AMR, EVRC, noise reduction, beam-forming, and speech recognition.
Mature and robust Software Development Environment
The CEVA-TL3211 DSP core is supported by a complete software development, debug, and optimization environment in the form of the CEVA-Toolbox. The ability to program in C is essential for reducing development time and ensuring easy portability to future platforms. Furthermore, the development environment fully simulates the CEVA-TL3211's fully cached memory subsystem, which allows for cycle accurate application development and profiling.
CEVA-Toolbox includes libraries, a graphical debugger, and a complete optimization tool chain named CEVA Application Optimizer. The Application Optimizer enables automatic and manual optimization applied in the C source code.
The CEVA-TL3211 DSP core and CEVA-HD-Audio solution are currently available for licensing. For more information, contact email@example.com.
About CEVA, Inc.
CEVA is the world's leading licensor of silicon intellectual property (SIP) DSP cores and platform solutions for the mobile handset, portable and consumer electronics markets. CEVA's IP portfolio includes comprehensive technologies for cellular baseband (2G / 3G / 4G), multimedia, HD video and audio, voice over packet (VoP), Bluetooth, Serial Attached SCSI (SAS) and Serial ATA (SATA). In 2009, CEVA's IP was shipped in over 330 million devices, powering handsets from 7 out of the top 8 handset OEMs, including Nokia, Samsung, LG, Motorola, Sony Ericsson and ZTE. Today, more than one in every three handsets shipped worldwide is powered by a CEVA DSP core.
For more information, visit http://www.ceva-dsp.com or call 650/417-7976.
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|Publication:||CD Computing News|
|Date:||Feb 1, 2011|
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