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 SAN JOSE, Calif., March 29 /PRNewswire/ -- Cadence Design Systems Inc. (NYSE: CDN) today announced the industry's first timing-driven crosstalk analysis product for design engineers of multichip modules (MCMs) and printed circuit boards (PCBs). Cadence's Design For/Signal Integrity(TM) (DF/Signal Integrity(TM) is the first product that incorporates timing information to predict crosstalk for real-world accuracy.
 Before today's announcement, all commercially available crosstalk tools made the flawed assumption that all adjacent signals switch simultaneously. This incorrect assumption not only exaggerates the crosstalk values, but also falsely predicts as many as half the nets on a board to have failed a crosstalk noise threshold, when the actual number of problem nets is usually much smaller. Consequently, engineers identifying the real problems from reams of predictions have a discouragingly tedious task -- a major reason why these tools have not been adopted in many design environments. With timing-driven crosstalk, DF/Signal Integrity eliminates these issues, enabling engineers to use signal integrity tools as part of the mainstream design process.
 Real-World Accuracy
 In the real world, many signals switch out of phase with each other, thus their crosstalk contribution on a given net is also out of phase. Additionally, on most data nets, receivers are sensitive to crosstalk only during the set-up-to-hold time window. Crosstalk outside this time window can be ignored. Accounting for this timing behavior results in more accurate crosstalk predictions. "Until now, all crosstalk tools have been blind to the design-specific timing behavior," said Jeff Grant, senior design engineer at Harris. "By taking advantage of a timing-driven implementation, we should be able to eliminate hundreds of false alarms and identify the handful of nets that truly have crosstalk violations."
 The DF/Signal Integrity product has been integrated with both Cadence's logic simulation and design entry environments to incorporate timing information in the analysis. DF/Signal Integrity uses the constructs of signal active time and receiver sensitive time to represent actual design-specific timing behavior. These along with the ignore crosstalk construct allow users complete flexibility to define timing at any stage of the design process. Signal timing is automatically forward-annotated from the Verilog-XL(TM) logic simulator to DF/Signal Integrity. Alternatively for design teams that don't use simulation, extension language programs can automatically generate these timing constructs within design entry, based on information such as clocking strategy. Once defined, these signal constructs are automatically used by DF/Signal Integrity.
 "The signal integrity market is still in infancy and we anticipate that it will grow significantly faster than the overall EDA market," said Bob Beachler, industry analyst for Dataquests' Worldwide EDA Market Research Service. "Signal integrity tools that accurately represent design behavior will be a key weapon in the engineer's arsenal to combat the true electromagnetic effects of high-speed circuits."
 CBD Approach
 DF/Signal Integrity's timing-driven implementation enhances the crosstalk-driven routing capabilities of the Allegro Physical Design System, a key part of Cadence's Correct-by-Design (CBD) methodology announced in February 1992. "Timing-driven" crosstalk routing enables users to make more accurate, less constrained design decisions that result in product cost savings. "Market acceptance of the CBD methodology has been tremendous," said Shiv Tasker, vice president of Cadence's System Physical Design group. "Only Cadence owns the core layout, simulation and analysis technologies required to provide this advanced capability to its users."
 Integration Architecture
 One of the characteristics of today's stand-alone signal integrity tools is their slow execution speeds. Cadence's DF/Signal Integrity uses an integration architecture that provides the required speed to perform interactive "what-if" design optimizations and analyze larger, more complex MCMs and PCBs. DF/Signal Integrity's integration architecture takes advantage of inter-signal timing information, including feedback on which adjacent signals are active during a current signal's sensitive time window, and subsequently, dramatically speeds up the analysis cycle. Additionally, the performance of the DF/Signal Integrity transmission line simulator has also been increased by up to two orders of magnitude through circuit optimization and adaptive time-stepping algorithms.
 Product Availability
 Cadence design solutions are supported on industry-standard UNIX workstations and servers from leading suppliers including Digital Equipment Corp., Hewlett-Packard, IBM and Sun Microsystems. DF/Signal Integrity is available now on all supported platforms and is (U.S. list) priced from $21,000 to $45,000 depending upon the desired software configuration. DF/Signal Integrity's new timing-driven crosstalk capabilities will be available in Q2 '93 and are provided at no charge to DF/Signal Integrity customers on software maintenance.
 One of the 10 largest software companies in the world, Cadence Design Systems Inc. is the worldwide leader in the development and marketing of design automation software and services that accelerate and advance the process of designing electronic systems. Cadence combines leading-edge technology with a complementary set of services that enable customers to improve the quality and time-to-market performance of innovative electronic products. Cadence is based in San Jose, and employs over 2,400 people in more than 60 R&D, sales and support locations worldwide. The company is listed on the New York Stock Exchange under the symbol CDN.
 NOTE: All Cadence products referred to are trademarks or registered trademarks of Cadence Design Systems Inc.
 -0- 3/29/93
 /CONTACT: Laurel Stanley of Cadence, 508-256-2300, ext. 247; or Toni Giusti of Cunningham Communication, 408-764-0737, for Cadence/

CO: Cadence Design Systems Inc. ST: California IN: CPR SU: PDT

SG-LM -- SJ010 -- 0495 03/29/93 11:53 EST
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Date:Mar 29, 1993

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