# Boost H-bridge inverter with reduced hardware configuration for harmonic minimisation.

INTRODUCTIONThe numerous advantages of multilevel inverters [1-10] fixes their chairs in new energy sources and industrial drive applications. However, the recital features of these multilevel inverters are decided by the pulse width modulation strategy used., The SHE-PWM strategy is mostly preferred among the existing trendy PWM techniques for minimizing the lower order harmonics in the output voltage waveform of the multilevel inverter. To express the staircase output voltage waveform produced by these inverters, many methods are introduced afterwards. The staircase voltage output waveform is made into a set of transcendental and non-linear equations using Fourier series expansion [2- 4, 8]. The main constraint in solving these equations is its firing angles. For solving these nonlinear equations, the lower order harmonics present in the output voltages are made to be at zero level by retaining its fundamental component at a preset level [2-10]. In many literatures, the SHE PWM technique has been reported due to its manifold advantages for the fundamental frequency operation of multilevel inverters with isolated sources [3, 4, 7-9]. To decompose the PWM current waveform or voltage waveform, the SHE-PWM strategy exploited the Fourier theory. The important properties of this waveform like unipolar, bipolar, and staircase nature derive this formulation. The other considerable properties of this waveform such as like or unlike source voltage levels, quantity of output voltage levels and uniformity are studied as further analysis. These properties determine the complication and the structure of the solution space. It is very tedious to find the proper algorithm for solving the SHE-PWM waveform. In the past, various strategies like classical resultant theory, iterative techniques and some evolutionary algorithms like Genetic Algorithm (GA), Differential Evolutionary (DE) algorithm and Particle Swarm Optimization (PSO) [2, 3] have been reported for formulating this waveform. Initially, these strategies are implemented for the conventional converters and then they extend to a range of multilevel and hybrid multilevel converters for the purpose of different applications. The author [2] applies Flower Pollination based Algorithm (FPA) to solve the firing angles for SHE-PWM strategy and also verifies the results produced by his methodology with the results generated by Particle Swarm Optimization (PSO) [3] and Genetic Algorithm (GA). Taghizadeh et al [3] solves the non-linear and transcendental equations for an 11-level inverter with dissimilar sources using PSO based algorithm and verifies their results with the results of FPA algorithm [2]. To provide a large number of output levels without increasing the number of cascaded H-bridges, a new inverter topology known as Boost H-Bridge inverter (BHBI) with a minimized number of hardware elements is designed with selective harmonic elimination PWM applied as a switching technique is proposed in this paper. The previously solved cascaded H-bridge multilevel inverter technique is compared with this new technique. Switch optimization using Boost H-bridge inverter in the following section. In H-bridge cascaded inverter, each level corresponds to one H-bridge which in-tum needs four switches, for a (2S+1) level of an inverter, it needs 'S' number of H -bridges and '4S' number of switches. This increased number of switches also need an isolated DC source and individual isolated driver boards. This above problem is overcome by an invited solution named Boost H-Bridge Inverter which provides the optimum number of switches for any level of output voltage. Due to this proposed scheme, there is a flexibility of design and also it optimizes design parameters such as reducing the number of DC voltage sources, number of either MOSFET or IGBT switches, requirement of gate driver circuits and high frequency power diodes. Minimized number of switches results in reliable topology with simpler control strategy, compact in size and improved efficiency. It is clear from the above discussion that this converter configuration can generate several levels with minimum number of components.

Problem formulation:

In general, a (2S+1) level of an inverter needs 'S' number of isolated DC sources. The cascaded H-bridge configuration needs [(n--t) / 2] a number of isolated DC sources for attaining 'n' number of levels. If suppose, it is not possible to have more number of sources, then it is required to find a suitable alternate topology for attaining more levels to eradicate the harmonic content present in the output voltage waveform. The main idea in the proposed Boost H-bridge inverter topology is to have a single DC source instead of a multiple isolated DC sources and a single H-bridge for attaining any number of levels.

Implementation of Selective Harmonic Elimination for the Proposed Boost H-Bridge Inverter:

The stair case waveform of a multilevel inverter is obtained using a single boost converter with one Hbridge. The different isolated DC voltages are obtained by varying the duty cycle of the boost converter. And the DC-link voltage across the capacitor is alternated using the H-bridge. A N-level of output voltage, it is required to have [(n--l)/2] number of duty ratio [[alpha].sub.(N-1)/2]. The following equations (1) and (2) represents the expression for [V.sub.dclink] and duty ratio respectively.

[V.sub.dclink] = [N-1/2.summation over (j=1)] [V.sub.dc]/(1 - [[alpha].sub.j]) (1)

[alpha] = [T.sub.on]/[T.sub.on] + [T.sub.off] (2)

Where, [alpha]- Dutycycle [V.sub.dclink] - DC-link Voltage across the capacitor [V.sub.dc] - Input voltage to boost converter [T.sub.on] - ON time of switch [T.sub.off] - OFF time of switch

The transcendental form of the Fourier series expansion of output staircase voltage is given as [2-3] and combining equations (1) and (2) the output voltage is expressed in the following equation (3)

V([omega]t) = [[infinity].summation over (n=1, 3, 5)] [4/n[pi] ([N-1/2.summation over (j=1)] [V.sub.dcj]/1-[[alpha].sub.j] cos (n[[beta].sub.j))] (3)

Switching angles [[beta].sub.1] - [[beta].sub.j] must satisfy the following condition:

0 [less than or equal to] [[beta].sub.1] [less than or equal to] [[beta].sub.2]... [less than or equal to] [[beta].sub.5] [less than or equal to] [pi]/2 (4)

0 [less than or equal to] [[alpha].sub.j] [less than or equal to] 0.9 (5)

[[alpha].sub.1] cos([[beta].sub.1]) + [[alpha].sub.2] cos([[beta].sub.2]) + ... + [[alpha].sub.5] cos([[beta].sub.5]) = [pi]/2 M (6)

[[alpha].sub.1] cos(5[[beta].sub.1]) + [[alpha].sub.2] cos(5[[beta].sub.2]) + ... + [[alpha].sub.5] cos(5[[beta].sub.5]) = 0 (7)

Where, Modulation index defined as M = [V.sub.1]/5[V.sub.dc] and [V.sub.1] is the fundamental voltage.

The stair case waveform of output voltage is expressed in equations (4) - (7), these nonlinear transcendental equations with trigonometric angles will not be solved in a classical way. The tedious and time consuming classical approaches is avoided using the versatile evolutionary based algorithms GA and FPA [2]. The Table. 1 provides switching angles for the equations (4) - (7). The angles [[beta].sub.1] - [[beta].sub.5] are solved using both GA and FPA for the duty ratio of [[alpha].sub.1] - [[alpha].sub.5]. The author [2] provide the detailed analysis of the results produced by both GA and FPA for various modulation indices. Based on that analysis, the best switching angles may be chosen from the following table. 1.

Switch optimization:

For a reduced THD level an increased number of voltage levels are needed. In case of a CHB inverter '4S' number of switches involving a n-level of output which is equal to '(2S+1)', where 'S' is isolated DC source. Say for a seven level inverter 'S' is equal to three and the number of switches needed is twelve. Out of twelve switches six switches come in contact during the positive and negative peak, which are connected in series. The on-state resistance ([r.sub.ds-on]) comes in the series is an appreciable amount of value for a higher load current. This will make high on-state losses as well as a higher amount of heat dissipation in the switches. The increased number of switches also involved in a considerable amount of space in the PCB layout in an inverter circuit and also requires individual driver boards. This spacing and wiring also hinders the aesthetic look of an inverter. Reliability is the other aspect which will always come in parallel with simplicity. To avoid all the above mentioned criteria that is the mandatory design of an inverter with minimal number of switches. The proposed BHBI have the inherent advantages of a single converter with one H-bridge inverter, so the structure is simple, elegant and reliable.

Proposed Inverter Topology:

The proposed scheme consists of a single stage boost converter for the multilevel DC stage with H- bridge inverter for alternating the multilevel DC stage is given in figure.1.

A solid state high frequency MOSFET switch for its converter stage and four IGBT switches for the Hbridge inverter. The DC link capacitor has the multilevel DC voltage across its arm by varying the duty cycle of the boost converter. This DC-link capacitor voltage is alternated for a power frequency of 50HZ using the Hbridge arm. The DC-link voltage produced across the H-bridge can be varied by varying the value of '[[alpha].sub.j]' mentioned in the expression (1). There are five numbers of duty ratios say, [[alpha].sub.1], [[alpha].sub.2], [[alpha].sub.3], [[alpha].sub.4] and [[alpha].sub.5] are required for attaining 11-levels at the output of the inverter. The optimum values of switching angles [[beta].sub.1], [[beta].sub.1], [[beta].sub.1], [[beta].sub.1] and [[beta].sub.1] are chosen from the table. 1, which is obtained using an evolutionary algorithm GA and flower pollination algorithm (FPA). In the conventional CHBI configuration, the four switches T1-T4 in the H-bridge are used to control the direction of current flow and hence produces an alternating output across the load. So it is very well evident that a 'n' level inverter needs a single boost converter with a single DC source instead of a '[(n-1)/2]' number of isolated DC sources. A single MOSFET for entire DC level building instead of a '[(n-1) /2]' number of MOSFET switches for DC level building of the CHBI configuration and single H-bridge only are needed for the proposed BHBI configuration. It needs a '[(n-1)/2]' number of duty ratio ([[alpha].sub.1], [[alpha].sub.2, ..., [[alpha].sub.(n-1)/2]]), for the boost converter and optimum switching angles ([[beta].sub.1], [[beta].sub.2], .... [[beta].sub.(n-1)/2]) to the H-bridge. The switching configurations of both CHBI and BHBI showing the number of H-bridges, the number of driver boards and total number of switches is given in the table.2. It is obvious from the table BHBI have the much reduced number of switches as well as a MOSFET driver board requirement compared to the CHBI inverter. Out of twenty switches used in CHBI ten switches come in series for each cycle of positive and negative alternation of output voltage.

MOSFET IRF840 is having '[R.sub.dson]' of 0.850[OMEGA], the resistance seen from the output terminal in either half cycle is 8.5 Q. This appreciable increase in resistance seen by the output will provide on-state losses of '[i.sup.2] x 8.5 W'. It is not an insignificant amount of losses in an inverter. This drop of voltage across the switches is evident from the result shown in figure.2. The list of hardware components is shown in the table. 3.

The solid state switch used in the boost converter is IRFP250N and its [r.sub.dson] value is 0.075[OMEGA]. The IGBT usually has lower on-state losses compared to MOSFET. In each half cycle only two switches come in the series, the typical forward voltage drop across the IGBTs is only 2 V. So totally 4 Volts are reduced in the terminal voltage compared to significant voltage drop across the MOSFET switches which is well evident from the output shown in figure 3.

RESULTS AND DISCUSSION

The simulation results were shown in figure 2 - figure 3 and hardware results have been given in figure 5.a and 5.b. Figure.2.a. Output waveform of CHB11-level inverter Figure.2.b. FFT analysis for CHB11-level inverter The results of CHB inverter and its corresponding FFT is given in figure 2.a and 2.b respectively. From the figures it is noted that all the selective harmonics ie., 5, 7, 11, 13 are eliminated except the triplen harmonics. In the three phase circuit configuration, triplen harmonics becomes zero [2]. The simulation results for the BHBI inverter is shown in figures 3-4. Compared to CHBI the THD levels are gradually reduced for the BHBI configuration. The lowest level of THD is achieved in BHBI compared to the other circuit for the given output voltage. The benefits of switch reduction and driver board requirements are given in table 2. Figure 5.a - 5.b illustrates the hardware results which show switching transients in each level changing point of an output waveform.

Compared to other configuration this will have predominantly had transient behavior in the output waveform. A specific value of filter components L and C reduces the harmonics as well as transients present in the output waveform which is shown in figures 4.a and 4.b. The hardware requirements for the two configurations are illustrated in figure 6. The proposed BHBI have the least number of component counts compared to other.

Conclusion:

The SHE-PWM algorithm is implemented using the evolutionary based genetic algorithm (GA) and flower pollination algorithm (FPA). These two techniques have been implemented in the Boost H bridge inverter (BHBI) configuration. This switching algorithm has removed selective harmonics such as 5, 7, 11, 13 for both the topologies and the benefits of the two schemes are analyzed. It is concluded that this proposed system has optimized the following parameters such as a reduction in the number of IGBT/MOSFET switches, isolated DC voltage sources, driver board requirements. This algorithm with inverter configuration has been given design flexibility and reduced number of the switches and driver boards which leads to the compact in size, reliability and improved efficiency with simpler control strategy.

REFERENCES

[1.] Reddy, B. Dastagiri, et al., 2015. "Embedded Control of n-Level DC-DC-AC Inverter." IEEE Transactions on Power Electronics 30.7: 3703-3711.

[2.] Srinivasan, S., and R. Ganesan, 20160 "Flower Pollination Algorithm based Selective Harmonic Elimination PWM for an Eleven Level Inverter." Asian Journal of Research in Social Sciences and Humanities, 6: 69-84.

[3.] Taghizadeh, H., and M. Tarafdar Hagh, 2010. "Harmonic elimination of cascade multilevel inverters with non-equal DC sources using particle swarm optimization." IEEE Transactions on Industrial Electronics 57.11: 3678-3684.

[4.] Jose Rodriguez and Jih-Sheng Lai, 2002. "Multilevel Inverters: A survey of topologies, controls, and applications" IEEE Transactions on Industrial Electronics, 49: 4.

[5.] Mariusz Malinowski and K. Gopakumar, 2010. "A Survey on Cascaded Multilevel Inverters", IEEE Transactions on Industrial Electronics, 57: 7.

[6.] Khaled El-Naggar and Tamer H. Abdelhamid, 2008. "Selective harmonic elimination of new family of multilevel inverters using genetic algorithms", Energy Conversion and Management, 49: 89-95.

[7.] Kavousi, Ayoub, et al., 2012. "Application of the bee algorithm for selective harmonic elimination strategy in multilevel inverters." IEEE Transactions on power electronics 27(4): 1689-1696.

[8.] Fei, Wanmin, Xiaoli Du, and Bin Wu, 2010. "A generalized half-wave symmetry SHE-PWM formulation for multilevel voltage inverters." IEEE Transactions on Industrial Electronics 57(9): 3030-3038.

[9.] Maia, Helder Zandonadi, et al., 2013. "Adaptive selective harmonic minimization based on ANNs for cascade multilevel inverters with varying DC sources." IEEE Transactions on Industrial Electronics 60(5): 1955-1962.

[10.] Ahmadi, Damoun, et al., 2011. "A universal selective harmonic elimination method for high-power inverters." IEEE Transactions on power electronics 26(10): 2743-2752.

(1) Srinivasan S, (2) Ganesan R, (3) Srinivasan A

(1) Assistant Professor, Department of EEE, Sethu Institute of Technology, Kariapatti- 626 115, Tamilnadu, India. (2) Professor, Department of EIE, Saveetha Engineering College, Thandalam, Chennai- 602 105, Tamilnadu, India. (3) Professor, Department of EEE, Sethu Institute of Technology, Kariapatti- 626 115, Tamilnadu, India.

Received 28 January 2017; Accepted 22 May 2017; Available online 28 May 2017

Address For Correspondence:

Srinivasan S, Assistant Professor, Department of EEE, Sethu Institute of Technology, Kariapatti- 626 115, Tamilnadu, India.

Caption: Fig. 1: Simulation diagram of Boost H Bridgell-level inverter

Caption: Fig. 3. A: Output waveform for BHBI 11-level inverter

Caption: Fig. 3.b: FFT analysis for Boost H-Bridge-11-level inverter

Caption: Fig. 4. A: Voltage waveform for Boost H Bridge 11-level inverter with filter

Caption: Fig. 4. B: FFT analysis for Boost H Bridge 11-level inverter with filter

Caption: Fig. 5.a: Hardware results of Boost H-Bridge Inverter

Caption: Fig. 5. b: Voltage waveform for Boost H-Bridge Inverter

Caption: Fig. 6: Comparative chart of different inverter configurations

Table 1: Switching angles for GA and FPA algorithms Modulation GA Index [[beta].sub.1] [[beta].sub.2] [[beta].sub.3] 0.50 36.66 52.50 64.52 0.70 6.80 18.43 33.02 0.80 8.76 22.51 38.76 1.00 6.49 15.69 25.39 1.075 3.18 11.74 20.65 Modulation GA FPA Index [[beta].sub.4] [[beta].sub.5] [[beta].sub.1] 0.50 82.46 89.98 38.08 0.70 89.91 89.94 12.21 0.80 59.08 88.53 8.24 1.00 38.50 57.95 3.20 1.075 28.52 42.94 3.97 Modulation FPA Index [[beta].sub.2] [[beta].sub.3] [[beta].sub.4] 0.50 56.42 66.43 81.39 0.70 34.04 50.50 68.94 0.80 21.99 38.38 59.01 1.00 15.12 20.71 32.85 1.075 10.33 23.44 30.42 Modulation FPA Index [[beta].sub.5] 0.50 88.12 0.70 90.00 0.80 88.86 1.00 51.84 1.075 42.60 Table 2: Comparison of both CHBI and BHBI configurations S.No. Type of inverter No. of No. of switches H-Bridges 1 Cascaded HB Inverter 5 H bridges 20 2 Boost H Bridge Inverter 1 H bridge 5 S.No. No. of driver boards 1 10 2 3 Table 3: List of Hardware Components for BHBI S.No Components Details of Components 1 IGBT FGA25N120 ANTD 2 Driver IC TLP 250 3 MOSFET IRFP 250N 4 Boost Inductor core EE55 5 Input DC capacitor 1000 [micro] F/250 V 6 Floating supply gate driver 12-0-12/200mA 7 Gate drive voltage +15 V/0 V

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Author: | Srinivasan, S.; Ganesan, R.; Srinivasan, A. |
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Publication: | Advances in Natural and Applied Sciences |

Date: | May 1, 2017 |

Words: | 3086 |

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