Bluespec Inc. Announces General Availability of Bluespec Compiler and Bluespec Simulator.
WALTHAM, Mass.--(BUSINESS WIRE)--June 1, 2004
Toolset Creates New Level of Abstraction for ASIC and FPGA Engineers,
Enabling EDA to Keep Pace With Moore's Law
Bluespec Inc. (www.bluespec.com) today announced general availability of its SystemVerilog-based Electronic Design Automation (EDA) toolset that creates a new level of abstraction for ASIC and FPGA engineers to control the growing design complexities involved with large-scale digital systems designs. In limited release since January 2004, the toolset enables for the first time high-level hardware synthesis with Quality of Results (QoR) that match hand-coded Register Transfer Level (RTL), accelerating the time to a verified netlist by as much as 50 percent and dramatically reducing verification efforts.
"Our toolset attacks the issues that are preventing design capability from realizing the full potential of Moore's Law," said Shiv Tasker, Bluespec CEO. "For the first time, our toolset delivers the productivity promises of high-level synthesis without the compromises."
The toolset wraps SystemVerilog around Term Rewriting Systems (TRS)-based synthesis, a groundbreaking technology developed at Massachusetts Institute of Technology (MIT) that enables control logic generation on a correct-by-compiler construction basis. The combination allows engineers to significantly raise the level of abstraction in design of ASICs and FPGAs while retaining the ability to automatically synthesize high quality RTL, without compromising speed, power or area. Bluespec further accelerates the overall product development cycle by delivering from a single high-level source both the RTL and a cycle-accurate C model that can be used for system level verification.
"The dramatic rise in complexity of leading-edge designs has been placing an undue burden (in terms of time, resources and expenses) on the front-end of the design process," said Erach Desai, electronics analyst for American Technology Research. "Bluespec is one of the few companies that are taking on the explosion in complexity found in today's chips, with a unique and cohesive approach towards front-end design productivity."
With a much higher level of design abstraction and the capability to generate both RTL and C, Bluespec offers a new design paradigm using SystemVerilog and assertion-based design. Designers have the option of working at different levels within the same environment: from transaction level simulation and debug down to a specific hardware implementation. A higher level of abstraction also ensures no premature freezing of architectural choice and allows more rapid timing closure. For the first time, Bluespec offers a unified design environment where designs can be architected, modeled, rapidly evaluated, and hardware generated.
Bluespec Product Data
Bluespec's tools sit directly in front of current design flows. The designer specifies the implementation at a high-level as System Verilog design assertions and generates Verilog output or cycle accurate C. Bluespec is completely interoperable with Verilog-based designs. Bluespec can easily incorporate Verilog IP - alternatively, Bluespec can be used within Verilog implementations. The toolset consists of two components: Bluespec Compiler and Bluespec Simulator.
Bluespec Compiler (BSC) includes the following compiler capabilities:
-- SystemVerilog language with Bluespec design assertions
-- Correct-by-compiler construction of control and datapath logic
-- Generation of no-compromise Verilog 95 RTL
-- Integrated, comprehensive static verification of designs to
eliminate problems before simulation
-- Code succinctness and static elaboration for high-level
abstractness and 10:1 code compression for large designs
-- Integrates existing Verilog IP and easily integrates into
-- Simplifies the integration of IP and creation of high-reuse IP
-- Rich library of design building blocks
-- Integrated compiler algorithms and techniques:
-- Modular compilation and design
-- Automated and user-defined scheduling of hardware
-- Scheduling visualization and feedback
-- Resource assignment, optimization
-- Standard optimizations, including common sub-expression
elimination and logic
Bluespec Simulator (BSIM) includes the following simulation capabilities:
-- Cycle accurate C-based simulation of the high-level design
-- 100% cycle accurate with Verilog
-- Full visibility to Bluespec source, interfaces, state elements
and design assertion rules
Both tools are designed and tested to work on Linux Red Hat versions 7.2 and 8.0.
The toolset is shipping now.
Bluespec Inc. manufactures an industry standards-based Electronic Design Automation (EDA) toolset that significantly raises the level of abstraction for hardware design while retaining the ability to automatically synthesize high quality RTL, without compromising speed, power or area. The toolset allows ASIC and FPGA designers to significantly reduce design time, bugs and re-spins that contribute to product delays and escalating costs. More information can be found on www.bluespec.com or by calling 781-250-2200.
Copyright 2004 Bluespec, Inc. Bluespec is a trademark of Bluespec, Inc. All other brands, products, or service names may be trademarks or service marks of the companies with which they are associated.
|Printer friendly Cite/link Email Feedback|
|Date:||Jun 1, 2004|
|Previous Article:||Atlas America, Inc. IPO Underwriters Exercise Over-Allotment Option.|
|Next Article:||DrugStor from Datum Filing Systems.|
|ETNUS TOTALVIEW TO SUPPORT IA-64 AND INTEL COMPILERS FOR LINUX.|
|New Green Hills C/C++ compiler: smallest code footprint for ARM processor family.|
|Bluespec Adds SystemVerilog Assertion Support as It Continues to Build Comprehensive ESL Solution.|
|Bluespec Wins 2006 DesignVision Finalist Award; Bluespec ESL Synthesis Chosen as Finalist in the ASIC, IC Design Tools Category.|
|Bluespec Momentum Grows as Leading Mobile Semiconductor Firms Adopt Its ESL Synthesis; Applications Range from Baseband Processor to Controller and...|
|Bluespec Executives to Participate This Week in DesignCon Tutorial Session, Management Forum.|
|Bluespec Plugs ESL Synthesis Hole in SystemC; Open ESL Synthesis Extensions to SystemC Create Unified Environment for Modeling, Design, Verification.|
|Bluespec Moves into Virtual Prototyping for Software Development, Hardware Validation.|
|Bluespec Begins Volume Shipment of SystemC Synthesis.|
|Bluespec Adds System-Level Building Blocks to AzureIP Foundation Library.|