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Azul Systems Selects ChipEDA ChipMason Design Flow and its Vraute Global Route Technology to Integrate its State of the Art 90nm 48 Core Vega(tm) 2 Processor.

SAN JOSE, Calif. -- ChipEDA, a provider of EDA tools and services, today announced that Azul Systems, a global provider of enterprise server appliances, licensed the ChipMason Design Flow and its vRAute(tm) technology to integrate its state of the art 48 core, Vega(tm) 2 processor. Azul announced the industry's largest multicore chip was in their labs back in March 2006 (http://www.azulsystems.com/press/032706_vega2.htm)

"By selecting ChipEDA's hierarchical design flow, we were able to achieve design closure while cutting implementation costs significantly," said Paul Koike, Sr. Director, Silicon Engineering at Azul Systems. "ChipEDA's hierarchical layout re-use flow in conjunction with their global route capability, made the problem of integrating a very large chip, with aggressive timing goals manageable by a small design team, allowing us to achieve timing closure."

"ChipEDA's hierarchical design flow with built in timing closure and layout re-use enables our customers to build an entire product line around a core technology in record time with minimal resources. By adopting ChipMason, Azul Systems was able to increase their functionality on chip and their timing goals, while keeping design costs and schedule under control," said Fuad Abu Nofal (Founder and Principal Engineer).

About Azul Systems

Azul Systems is a global provider of enterprise server appliances that delivers compute and memory resources as a shared network service for transaction-intensive applications, such as those built on the Java(tm) platform. Our family of Azul Compute Appliances enables transparent, massively scalable infrastructure that supports the business priorities of today's most demanding enterprise environments and delivers increased capabilities, capacity and utilization at a fraction of the cost of traditional computing models.

About ChipEDA

"ChipEDA" is a provider of EDA tools and services for chip floor planning and rapid silicon prototyping. "Chipmason" EDA tool set, supports package/chip co-design, hierarchical design flow and layout re-use methodology.

Design ReUse is an essential part of the Chipmason feature set. Any block designed using Chipmason can be reused multiple times in the same chip or across multiple chips. Pin assignment of the block is done with reusability in mind. Through its unique global route technology Vraute, Chipmason allows designers to plan upfront the buffering of their global wires and to route/time the top level of the chip while the underlying blocks are still under construction. Thanks to a "correct by construction" approach, this methodology solves the design issues of global timing convergence and layout reuse.

Power is generated using Chipmason to allow the block to be connected to the top level power grid without modifications, regardless of the structure of the top level power grid. Chipmason users tackle multi-million instance designs efficiently and gain significant cost reduction in their product development and shorter time to market.
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Publication:Business Wire
Date:Nov 14, 2006
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