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Avant! to Acquire ACEO.

VHDL and Verilog Logic Synthesis Software Vendor Broadens Avant!'s SinglePass

VDSM Design Flow

FREMONT, Calif., Oct. 1 /PRNewswire/ -- Avant! Corporation (Nasdaq: AVNT) today announced the acquisition ACEO Technology, Inc., a six-year old privately held company. Details of the acquisition were not disclosed.

"The acquisition of ACEO gives Avant! the opportunity to fully develop what is known as the virtual RTL prototype," said Gerald C. Hsu, chairman, president, and CEO of Avant! Corporation. "With our strategic acquisitions we have established a solid base for next-generation tool development to solve the design paradigms of the future. Now synthesis can be merged with front-end design planning and physical design in the VDSM era. Avant!'s common environment for RTL design planning, synthesis, as well as place and route, will facilitate the development of fundamentally new methodologies."

ACEO's technology is a complete set of fast, high-performance hierarchical synthesis tools that accommodate extremely high gate count of very deep submicron (VDSM) designs. ACEO pioneered the One Pass Hierarchical Synthesis that automates and eliminates manual time budgeting for very large designs, and Layout-Driven Synthesis that provides a preview of the layout of VDSM designs. The purchase of ACEO will further Avant!'s pioneering work on Saturn's VDSM optimization that combines static timing analysis, logic optimization, and layout optimization into a single, automated tool to eliminate timing convergence problems caused by limitations in traditional synthesis technology.

"The collaborative technology development environment at Avant! has produced a number of innovations -- that was the most significant incentive for our joining the company," said Dr. Ray Wei, president and CEO of ACEO Technology. "ACEO's proven synthesis technology clearly complements Avant!'s robust SinglePass methodology. Avant!'s fertile environment should produce the combined synthesis and layout linkage breakthrough in the area of design size, performance and timing that our customers so desperately need."

ACEO's logical synthesis tool enhances Avant!'s SinglePass VDSM methodology, which offers customers a packaged flow of RTL design through synthesis and place and route. Introducing ACEO's technology into the SinglePass design environment will improve productivity and allow the design of better and more complex chips.

"Avant! can now offer a uniquely comprehensive RTL VDSM design solution," said Dr. Chi-Ping Hsu, CEO Staff of products at Avant!. "The key synthesis technology from ACEO will complement the Saturn optimization and VDSM place and route technologies, as well as the unequaled power of Avant!'s SinglePass solution."

ACEO offers a complete line of VHDL and Verilog logic synthesis, ASIC/FPGA netlist migration, multi-FPGA partitioning, and rapid ASIC prototyping software products that are in production use in the PC chip-set design, consumer electronics, semiconductor, and communication industries. End products from these companies include multimedia, networking, and video compression ICs.

Avant! will continue to enhance and offer leading-edge technologies to the ACEO customer base.

About ACEO

ACEO Technology, Inc., the new synthesis solution, founded in August 1992 by Dr. Ruey-sing (Ray) Wei, is a privately held California-based company that pioneered One Pass Hierarchical Synthesis (OPHS) and Layout-Driven Synthesis (LDS) for advanced deep submicron designs. ACEO also provides ASIC design technologies for intelligent design migration and rapid ASIC prototyping. All products are available on UNIX and WindowsNT.

ACEO is headquartered in Fremont, California.

About Avant!

Avant! (pronounced ah VAHN tee) Corporation develops, markets, and supports integrated circuit design automation (ICDA) software for the design of deep submicron ICs including microprocessors, microcontrollers, application-specific standard products (ASSPs) and complex application-specific integrated circuits (ASICs). Avant!'s full tool suite covers process characterization, circuit simulation and analysis, HDL simulation, formal verification, floorplanning, physical design and VDSM optimization, interconnect parasitic extraction, timing simulation, and physical verification. Avant! also provides physical foundation IP libraries for integrated circuit design. Avant!'s tools support hierarchical design methodologies as well as incremental design changes in all phases, and they offer the capacity needed for multi-million transistor devices.

Avant! is headquartered in Fremont, California with offices worldwide. Tel 510-413-8000, Fax 510-413-8080

NOTE: Avant!, Planet-RTL, Polaris, and SinglePass are trademarks of Avant! Corporation. All other company and product names mentioned herein are trademarks or registered trademarks of their respective owners and should be treated as such.
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Publication:PR Newswire
Geographic Code:1USA
Date:Oct 1, 1998
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