An effective asynchronous micropipeline using double edge triggered D Flipflop.
This paper presents the design and simulation results of asynchronous micro pipeline using an effective Double Edge Triggered D Flip-Flop (DETDFF). Here an attempt has been made to construct an asynchronous micro pipeline using the proposed DETDFF with an aim to have low power consumption and delay. The performance of the proposed circuit in terms of Power consumption and delay is compared with Asynchronous Micropipelines constructed using other DETDFFs. The circuits were simulated using TSPICE in both 0.18p and 0.13p CMOS technologies for an operating frequency of 1Ghz. The simulation results shows that the micropipeline desined using the proposed DETDFF consumes low power and has lower delay.
Keywords: VLSI, Asynchronous, Micropipeline, CMOS, DETDFF.
Asynchronous designs do not require global clock for synchronization. They are synchronized using event-driven communication in which transition on wires act to request the start of a computation and acknowledge its completion. By removing the global clock, asynchronous designs has the advantages of absence of clock skew problems, freedom from worst case design restrictions, and automatic power down of unused circuitry[1-2].
Micropipeline is based on a two phase transition signaling, event driven communication protocol in which an event is either a low-to-high or high to low transition on a control wire with no distinction being made between the two.
Since traditional latches are level sensitive, however, traditional designs required two-to-four and four-to-two phase converters, which hinder performance.
On replacing traditional latches by DETDFFs, will eliminate the need of phase converters. Also it reduces the time delay due to the latching of data in both transitions of clock. Thus asynchronous Micro Pipelines constructed using DETDFF will result in less complex control circuit and hence has significantly improved performance.
Designing of asynchronous Micropipelines using DETDFFs have been discussed in  and  and in this paper an attempt have been made to construct asynchronous micropipeline using the proposed double edge triggered D Flip Flop with an aim to achieve low power consumption and delay. Section 2, presents the design of asynchronous Micropipeline using Double Edge Triggered D Flip Flop. Section 3 discusses some of the earlier DETDFFs and section 4 describes the proposed DETDFF.
Section 5 presents the simulation results of the asynchronous micropipeline circuits using earlier DETDFFs and the proposed DETDFF. Finally the discussion and conclusion are drawn in section 6.
Implementation of Asynchronous Micropipeline using DETDFF
Pipelining is a standard way of decomposing an operation into concurrently operating stages to increase throughput at a moderate increase in area. A wide variety of applications such as digital filters, video compression and general purpose microprocessors, can all be decomposed into pipeline structures. Pipelines can be implemented both synchronously and asynchronously. In a synchronous pipeline the communication of data between stages is regulated by the global clock. It is assumed that each stage takes no longer than the period of the clock and data is transferred between consecutive stages simultaneously. In asynchronous pipeline the communication of data between the stages is regulated by local communication between stages. When one stage has data which it would like to send to a neighboring stage, it sends a request to that stage. If that stage can accept new data, it accepts the new data and returns an acknowledgment. The Key aspects of micropipeline strategy is the bundling constraint and request / acknowledgement communication protocol that governs the transfer of data between stages.
The transfer of data between stages in a micropipeline is based on a data bundling scheme. The interface stage i and stage i+1 includes a bundle of data which carries information and a request wire. When request wire rises and is scanned at stage i+1, then the stage i+1 assumes that a valid data is available at its inputs. An advantage of this approach is that it facilitates use of combinational data path blocks that may have been previously designed for use in synchronous circuits. Hence, the data path block can easily be placed between two communicating micropipeline stages. The request is sent after the data at the input of the combinational logic is valid. Because of the delay introduced by the buffer, it is sensed at the receiver only after the data is guaranteed to be stable at the receiver's input.
A simple two phase asynchronous pipeline circuit design using double edge triggered D flip flops as storage elements and a C--element to control each stage of the pipeline is shown in Figure 1.
This pipeline circuit is similar to Sutherland's Micropipeline, except that it uses double edge-triggered flip flops in place of capture-pass latches and relies on a simple set of timing constraints for correct operations.
[FIGURE 1 OMITTED]
Consider stage i whose inputs are [R.sub.in] and [bar.[A.sub.out]] and whose outputs are [bar.[A.sub.in]] and [R.sub.out]. When its left neighbor toggles [R.sub.in], signaling that the data [D.sub.in] is valid, stage is pipeline control toggles its output [bar.[A.sub.in]] (assuming that the previous request to the right neighbor has been acknowledged). Toggling of the control C--element acknowledges the receipt of data to its left neighbor, latches the data in stage is storage, and enables [R.sub.out] to toggle after a bundling delay (Muller C element output will be logic0 if both the inputs are 0 and the output will be logic l if both its inputs are 1. For other input conditions, Muller C will retain the previous output. The bundling delay is necessary to provide sufficient data setup time for stage i+1, i.e., [D.sub.out] of stage i must be valid before stage i+1's latch control toggles.
In practice, the latch control buffers incur significant delay and hence the data can be delayed accordingly. In that case, toggling of the request line means that the data will be available at the next stage after some delay. (roughly the same as the latch control buffer delay).
The next section gives brief description about the design and operation of the previously reported DETDFFs.
Here we have described three earlier reported DETDFFs designed by Gago, WaiChung and T.W.Kwan respectively.
The Gago's DETDFF is illustrated in Figure 2. Nodes N2, N3, N4, and N5 represent parallel connections between input buffers and latches. The appropriate phase of clock and its complement connects and disconnects the input buffers and storage elements from the power supply and ground.
The circuit has two portions upper half and lower half. Each stage in turn has two stages namely inverter stage and double inverted stage.
The upper half issues the output at negative edge and lower half at positive edge due to the node connections N2,N3,N4 and N4.
[FIGURE 2 OMITTED]
Wai Chung's DETDFF
The WaiChung's DETDFF circuit  shown
in Figure 3 has two stages, the left stage issuing output at the negative edge of clock and the right stage issuing output at positive edge. When one stage is in action, the other stage is deactivated The circuit operates using pass transistor logic.
[FIGURE 3 OMITTED]
Tin Wai Kwan DETDFF
The block diagram of MCML (MOS current mode logic) DETDFF proposed by T.W.Kwan is shown in figure 4. It consists of two opposite polarity level sensitive MCML latches and an MCML multiplexer. The input clock differential transistor pair puts the latches in either transparent mode or capture mode and routes the data stored in one of the latches to the global output. Even though the power consumption of this current mode logic DETDFF is said to be independent of frequency, the amount of power consumption is very high at lower GHz frequencies compared to CMOS logic circuits. The circuit is much suitable for multi GHz operating frequencies.
[FIGURE 4 OMITTED]
Figure 5 depicts the proposed DETDFF. According to the actual and complement values of clock, the two stages of the circuit latches data at the edges of the clock. In the proposed DETDFF If CLK=O and data input DIN=1, then both the NMOS in the INV2 inverter circuit are ON, and hence the node X is pulled down to 0. However the inverter INV3 will not respond until CLK remains 0. At the positive edge of the clock, the INV3 responds and since X= 0 the output Q will rise to 1.
For DIN=0 and CLK=0, both the PMOS in the INV2 inverter circuit are ON, and hence X rises to 1. At the positive edge of the clock, INV3 responds and since X=1, the output Q falls to 0. Until CLK remains in 1, the change in DIN will not have any effect over the output as INV2 will be inactive. Similarly the lower stage issues output at negative edge of the clock.
The inverters in the feedback path (INV4 and INV5) act as statizisers. For CLK=0, DIN= 1 and Q=1 condition, because of INV2, the node X will be pulled down to 0. But at the same time since Q=1, the INV4 try to pull up node X. However this situation can be mitigated by down sizing the transistors of INV4. For the similar reason , the transistors of INV5 are also weak transistors. Because of the perfect isolation of the active and inactive parts, the proposed circuit has low power consumption and has it has potential for low power applications.
Three stage Asynchronous micropipelines using the proposed DETDFF has been simulated and its performance is compared with the asynchronous micropipelines constructed using DETDFFs by Gago, WaiChung and Tin Wai Kwan. All the circuits were simulated using TSPICE for 0.13[micro] and 0.18[micro] CMOS technologies with operating frequency of 1GHZ.The supply voltage is taken as 1.3v for 0.13[micro] and 1.8v for 0.18[micro] CMOS technology. The power consumption and delay are the factors taken under consideration. The test set up shown in Figure 6 is used for all circuits. The power consumption for transferring 20 data bits through the micropipeline has been considered.
The delay what we considered here is the time taken for a data bit to appear at the output of a stage (here second Flip Flop) from its input, on receiving Request signal. The Rise time, fall time for all signals are kept as 0.1ns.
[FIGURE 5 OMITTED]
[FIGURE 6 OMITTED]
Transistor sizing for all the three circuits were carefully analyzed and appropriately selected to provide low power consumption.
The simulation results for 0.18[micro] technology and 0.13[micro] technology are given in Table 1 and Table 2.
The results shows that the Micropipeline implemented using the proposed DETDFF stands ahead in power consumption and delay compared with Micropipelines using Gago WaiChung and T.W.Kwan DETDFFs in both 0.13[micro] and 0.18[micro] CMOS technologies. In 0.13[mirco] technology the power consumption of the micropipeline using the proposed DETDFF is 24% less than Gago circuit , 4% less than WaiChung circuit and 52% less than T.W.Kwan DETDFF whereas in 0.18[micro] technology the power consumption of the proposed circuit is 58% less than Gago circuit, 41% less than WaiChung circuit and 74% less than T.W.Kwan circuit. The delay for the proposed circuit is less than the other micropipeline circuits for both 0.13[micro] and 0.18[micro] CMOS technologies.
Figure 7 shows the simulation output for the three stage 0.13[micro] based micropipeline using the proposed DETDFF. 20 bits of alternate is and Os are transferred through the micropipeline and from the wave forms we can see that the data bits are moving from one stage to another at each edge of Rin(Request) signal. Also the waveform shows the delay between Rin and data out at stage2 (ie., Q2) is 192.59ps.
Due to the perfect isolation of active and inactive parts of the circuit , the proposed circuit provides low power consumption on compared with Gago and WaiChung micropipelines. The power consumption of the current mode logic based T.W.Kwan circuit is very high in the lower GHZ frequencies. As the power consumption is more or less independent of frequency, the micropipeline using current mode logic DETDFF will be more appropriate for multi GHZ frequencies. The micropipelines using CMOS logic based DETDFFs (including the proposed circuit) suffers a drawback that its power consumption rapidly increases as operating frequency rises. Hence the micropipeline using the proposed DETDFF will be more appropriate for lower GHZ frequency applications.
The design and simulation of Asynchronous micro pipeline using an effective Double edge triggered D Flip-Flops had been carried out in this paper. The proposed asynchronous micro pipeline circuit has been compared with asynchronous micropipelines constructed using three other earlier DETDFFs and their performance in terms of Power consumption and delay were compared. The circuits were simulated using Spice for both 0.13[micro] and 0.18[micro] CMOS technologies . The results shows that the Micropipeline implemented using the proposed DETDFF has low power consumption and lower delay compared with Micropipelines using other DETDFFs. Hence the micropipeline designed using the proposed DETDFF has potential for low power applications.
[FIGURE 7 OMITTED]
 A. Brzozowski. C.J, H. Segar, "Asynchronous circuits", Springer-Verlag New York inc, 1995.
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 Tin Wai Kwan and Maitham Shams, "Design of Multi-GHZ micropipelined circuits in MOS current mode logic", proceedings of 18th IEEE International conference on VLSI Design 2005.
 Wai Chang, Timothy Lo and Manoj Sachdev, "A Comparative Analysis of Low-Power Low-Voltage Dual-Edge-Triggered Flip-Flops" IEEE Journal of VLSI Systems, Vol. 10 No.6, pp. 943-949, Dec 2002.
S. Kaja Mohideen * and J. Rajapaul Perinbam
Research Scholar (Anna University)
B.S.A. Crescent Engineering College, Chennai, India.
* E-mail: Skm email@example.com
Professor, Electronics Department, Anna University, India
Table 1: Simulation Results for 0.18[micro] Micropipeline Power Consumption ([micro]Watts) Delay (ps) Gago 356.6 236.3 Wai Chung 282.7 280.13 T.W.Kwan 554.24 262.63 Proposed 271.5 227.61 Table 2: Simulation Results for 0.13[micro] Micropipeline Power Consumption Cycle Time (ps) ([micro]Watts) Gago 75.19 200.3 Wai Chung 53.49 245.12 T.W.Kwan 119.09 273.13 Proposed 31.73 192.59
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|Author:||Mohideen, S. Kaja; Perinbam, J. Rajapaul|
|Publication:||International Journal of Applied Engineering Research|
|Date:||Jan 1, 2007|
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