An approach to design, simulate & synthesize frequency meter using VLSI technology.
Frequency is one of very important parameter of electrical signals. Now a days digital system have taken over from analog system for measurement & control functions. All digital functions operate at some frequency. Also many times the output of sensors is frequency modulated. Any analog signal can be frequency modulated by adding a VCO to the circuit & thus it can be represented in terms of frequency. This output in terms of frequency can be monitored by the frequency meter & the amplitude of the signal can be determined. The additional advantage achieved is that the data can be transmitted to remote locations in terms of frequency & is not corrupted by noise on the way. The frequency base signal can be easily retrieved & processed to get the data. The temperature sensors are available with output represented in terms of frequency. A simple LCR meter can be built by using components whose values are to be determined in an Oscillator circuit by measuring their values in terms of frequency. A frequency meter thus serves as a very useful tool for electronics engineer. As the maximum range of measurement 30 MHz is sufficient for most of the purpose of instrumentation hence the range of measurement of system was kept from 1 Hz to 30 MHz. how ever frequency range of operation can be enhanced by minor modifications. Since whole circuit is configured on a single chip hence reliability of the system is increased as system with more no of devices. As the number of parameters will be configured in terms of frequency the reprogrammability of the chip will allow the same system hardware to be configured as per the parameter to be measured.
I/P- TTL level
Frequency range: 1Hz to 30 MHz
Monitoring / control through PC
Data storage on PC
Diagram of Frequency Meter to be Synthesized on FPGA
This is a TTL buffer & protects the FPGA from external faults that may develop during the system operation the FPGA xilinx4005 also provides buffering to all the its inputs so that data inputs are not loaded the buffer also prevents from excess voltage. It also converts the input signal to rectangular pulses for processing by FPGA
Serial Communication Buffer
An RS232C is used to provide isolation from remote PC and to send & receive data from PC. This buffer also provides level conversions required for RS232-C link the received serial data is converted into TTL levels from RS232C levels after conversion the serial data is sent to the FPGA in the same format. The serial receiver transmitter block configured on FPGA converts the serial bit stream to parallel data.
The system is designed to provide 4 digit seven segment displays. This is achieved by synthesizing the circuit for one BCD COUNTER (which counts from 0 to 9) and then cascading four such counters to get the required functionality.
Counter synthesized on FPGA perform the following functions. It can be reset to zero by asserting a high on reset input. It can be enable and disable by setting enable to '1' or '0' respectively.
Latch and Decoder
The function of these devices is to store the information when measurement is over and present in form readable by user. When the measurement is over a latch pulse is generated. This pulse latches the data in four bit latches .Individual decoders at the output of each of these latches convert the data from HEX to seven segment format.
The controller is a sequential machine and it sequentially goes from present state to next state on completion of operation in the present state. Transition to the next state is determined from the present state. It does not depend upon on any of its inputs. There are three possible states of the controller: reset mode, measurement mode and display mode.
At any instant of time, the controller is in any one of the states. The system is first of all brought to reset mode state by giving a high on its asynchronous reset. In reset mode, it issues a reset pulse to reset all the counters to zero. Once the counter is reset to zero, the system can start the measurement process. The controller then goes to measurement mode state when reset pulse goes to zero. In measurement mode state, the counters are enabled by issuing a high (enable) on gate input and a low on reset input. The counter then gets enabled and starts counting. The counting is enabled for the duration determined by count_gate_length. The value of count-gate-length is variable and is automatically adjusted by the time base depending upon the input frequency to give maximum resolution in 4 digits. The controller simply reads the value of count-gate-length and enables the gate for that duration of time. The counter thus measures the input pulses for a fixed duration of time decided by count- gate-length. After the measurement mode state is over, the controller goes in display mode state when the gate goes to zero. In display mode state the measured value is latched by latch pulse and stored in latch decoders. This value remains in the latch till the next reading is available for display. Thus the display is continuously ON during the entire cycle.
During latch mode, the latched data is also serially transmitted to PC by word- Transmitter. When latch pulse is asserted, word transmitter starts transmitting data. The transmitted data is of the format (:)
Identifier Digit 1 Digit 3 Digit 4 Separator Pointer Count Length
A program specially written in visual basic for display of frequency data receives this data.
Identifier helps in determining the status of the data. Control character (CR) corresponding to binary data 00001101 is used to represent identifier. All digits are first converted to ASCII format. A colon (:) is used as separator. Pointer count Length (PCL) gives information about the range of frequency. This is also converted to ASCII format & transmitted. The display program written in visual basic captures the data, separates the digit & information. It thus converts this data to proper display format and then displays the frequency output.
After serial transmission of data is over, the controller reset each pulse to zero and goes from display to reset mode and the process is restarted. Reset pulse, gate pulse and latch pulse conform to these three states of controller and represent the status of the controller and represent the status of the controller at any instant.
Time base in the circuit provides the duration of on time of enable pulse. The duration of the enable is adjusted as per the input frequency to get the maximum resolution in 4 digits. To achieve this, the time base circuit gets information of last digit and overflow bit from the counter circuit.
The flow chart of time base is as
* If overflow occurs while measurement of frequency, it indicates that the gate length should be reduced. The gate length is then reduced by ten times. This means that the counter will count pulses ten times less than the previous count. In effect the display get the shifted by one digit to the right to overcome the overflow error.
* In case no overflow occurs and last digit has acquired some value, the time base needs not to be adjusted as the counter are already giving maximum resolution.
* In case no overflow occurs and the last digit also does not acquire some value the counter increases the on time of enable pulse by ten times. This has the effect of counting input frequency pulses more by ten times thus display gets shifted to the left by one digit and thus gives maximum resolution for that frequency.
The word transmitter decides the control characters required to be sent to the PC along with the data and accordingly prefixes these characters with the block of data to be sent.
The PC on receiving these control characters verifies the correctness of data and accordingly accepts and rejects data. The word transmitter transmits the information in bytes.
Simulation & Results
In a VHDL design process, the component or devices to be used are listed out. If the components already exist in component library, the components are already used from the library. After describing the components simulation is done.
The resulting data structure represents the digital system being simulated. After initialization phase, the simulator enters the execution phase. The simulator accepts simulation commands, which control the simulation of the digital system and specify the desired simulator output.
Actual Testing Calibration
The measurement of various pulse widths was done using a Tek- scope TDS220 having a sampling rate of 931sample/ sec. The oscillators used with system for maintaining time is of frequency 1Mhz.
It is being concluded that the design frequency meter has following sailent features
* It has the frequency range of measurement from 1 Hz to 30 MHz.
* It has the automation range of selection to give maximum resolution in 4 digits.
* The whole circuit is configured on a single chip hence reliability is increased as compare to the system with more number of devices.
 Xilinx, Altera, Actel Manuals for FPGA selection.
 Simtek, Cypress, Texas, Maxim Manuals etc for RAM & other component selection.
 Recent manuals of H.P., Tektrinix, National instruments.
 Charles H.Roth,Jr., "Digital system design using VHDL".
 FPGA Express VHDL reference manuals.
 J. Bhaskar, "A VHDL Primer".
 Chip Designing (Technology Focus) EFY July 2001.
 David Malinaik, "SOC design methods to meet the needs for speed", Electronics design April 2001,pp 76-86.
 The future of platform FPGA,s , page 23, Xcell journal, issue 40, summer 2001.
 Benefits of VLSI technology, EFY August, 2001.
 Active HDL 4.2 FOR VHDL code simulation.
 Xilinx foundation series 2.1 for synthesis and implementation.
(1) Abhay Sharma and (2) Bhupindra Singh Chabra
Deptt. Of ECE Green Hills Engineering, Kumarhatti (H.P), Deptt. Of Computer Science PEC Chandigarh E-mail: (1) email@example.com and (2) firstname.lastname@example.org
Measured Actual Error Error Frequency Frequency Percentage(%) 9.601 MHz 9.599 MHz .002 .02 4.801 MHz 4.799 MHz .002 .04 2.400 MHz 2.399 MHz .001 .04 1.200 MHz 1.199 MHz .001 .09 6006KHz 5993 KHz .0013 .20 3003 KHz 2999 KHz .0004 .10 1501 KHz 1499 KHz .0002 .13 750 KHz 749 KHz .0001 .13 375 KHz 374 KHz .0001 .26
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|Title Annotation:||very large scale integration|
|Author:||Sharma, Abhay; Chabra, Bhupindra Singh|
|Publication:||International Journal of Applied Engineering Research|
|Date:||Oct 1, 2009|
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