Adhesion of electroless copper to flexible circuit materials: total success is not achievable without a low stress electroless copper deposit.
When discussing adhesion of a deposited metal to a substrate, one must focus on two distinct but related processes. The first relates to surface preparation conditioning and the second to the deposition of the metal itself.
Preparing the Polyimide Surface
One common theme that electroplaters often notice is surface preparation. Materials such as polyimide are prone to low copper adhesion. To mitigate this situation, specially formulated conditioners are employed to provide a surface that is conducive to adhesion. Any surface that one desires to deposit another coating on requires that surface to be activated. Otherwise, defects are often found (FIGURE 1). These defects generally include blistering, peeling and voids.
[FIGURE 1 OMITTED]
One critical step in the process sequence is to utilize a conditioning agent (prior to electroless copper metallization) that makes the polyimide material more susceptible to adhesion of the palladium catalyst. In turn, the conditioning agent enhances the adhesion of the subsequently plated copper to the polyimide.
This technique of conditioning is designed to etch the polyimide film in such a manner as to increase the surface area of the film. In turn, the increased surface area improves adhesion of the subsequent copper metal. The technique utilizes an aqueous solution containing sodium hydroxide and hydrazine. When compared to test panels prepared without the chemical treatment, the treated polyimide specimens exhibit superior adhesion of the copper.
As is often the case, electroless copper plating process systems include a second conditioning step after polyimide etch. While this author recommends such a step, it is with reservation. Basically, the second conditioning step must contain materials that are free timing so as not to leave a film on the polyimide. Such a film may lead to a barrier that reduces adhesion of the copper deposit. Should such a situation arise, the fabricator would be better served to run a performance test with no extra conditioner, one with 50% of the recommended concentration and one test with the full recommendation. Then after plating, perform a tape test to quantify the adhesion, or lack thereof.
Electroless Copper Deposition
The importance of the conditioning step not withstanding, total success is not achievable without a low stress electroless copper deposit. Typically, deposited metals exhibiting a high degree of internal stress find it necessary to "pullaway" from the substrate in order to relieve the stress condition.
Literature reviews and basic research studies provide evidence that the grain structure of the copper deposit influences the deposit's adhesion to the copper interconnect. Microsections taken from test boards processed in different electroless copper process formulations show vastly varying structures. In FIGURE 2, the structure is one that is considered a finely grained crystal structure that appeared "loose." From multiple testing programs, this type of structure was more prone to hole wall pullaway and overall poor adhesion. The structure in FIGURE 3 has a high correlation to good interconnect reliability as determined by IST and thermal shock testing. In addition, this type of deposit structure exhibited very low stress and provides excellent adhesion when subjected to tape testing. It is highly recommended that for flex circuit applications, especially dynamic flex, maximum adhesion of the copper to the substrate be achieved. Further, the data supports the assertion that a low to medium deposition electroless copper process be employed for flexible circuit manufacturing. These types of electroless copper processes typically provide a low stress deposit with a fairly large grain structure as shown in Figure 3.
[FIGURES 2-3 OMITTED]
MICHAEL CARANO's vice president, Marketing and Business Development at Electrochemicals Inc.; mcarano@ electrochemicals.com.
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|Title Annotation:||POSITIVE PLATING|
|Publication:||Printed Circuit Design & Manufacture|
|Date:||Jun 1, 2007|
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