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Achieving impedance control targets: the standard tolerance for characteristic impedance of a line--[+ or -] 10%--is changing fast. Use of field solvers can get Zo within [+ or -] 1%.

The standard for the tolerance in characteristic impedance is [+ or -] 10%, but this requirement is being reduced to meet more difficult noise budgets. The only way to meet this goal is by applying engineering discipline to design and fabrication. This includes the use of accurate 2D field solvers, precision robotic testing, accurate dielectric constant characterization and attention to detail in each step of the manufacturing process.

The characteristic impedance (Zo) of a transmission line is one of two fundamental terms that fully describe it electrically; the other is time delay. In the system design process, choosing the optimum target value for Zo depends on a balance of cost/performance factors, such as driver capabilities, sensitivity to capacitive load delay adders, sensitivity to crosstalk from adjacent traces, sensitivity to switching noise, ground bounce, EMI, total board thickness and manufacturing cost.

Once the dielectric material and target impedance value is selected, which is typically between 45 [ohms] and 65 [ohms] for single-ended and 80 [ohms] to 120 [ohms] for differential lines (with the notable exception of Rambus boards with 28 [ohms]), the job of the fabricator is to achieve that target value and not exceed the specified tolerance range.

If the board and all its components have been designed for one value of impedance and the as-fabricated board comes back with a different impedance, signal quality distortions result. Keeping the impedance of all the traces on a board within the specified tolerance is part of signal integrity noise management.

If the impedance exceeds the tolerance, there is the potential for ringing and reflection noise. An example of the sort of reflection noise that might arise flora a line 10% off its tolerance and a series-terminating resistor also 10% off its tolerance is shown in FIGURE 1.

[FIGURE 1 OMITTED]

Although by itself the reflection noise from impedance mismatches between the board traces and any terminating resistors may not be large enough to cause an error, this is only one of more than a dozen terms that go into the noise budget. It may take only one term exceeding its allocated budget for the product to fail.

In high-speed serial links, lossy effects are becoming more important due to the collapse of the eye diagram. It can be opened up slightly by either using more expensive, lower loss dielectrics or tightening up the tolerance on Zo. This cost/performance tradeoff will be an important driver for tighter impedance control.

The industry standard for tolerance in the characteristic impedance of a line is [+ or -] 10%, and is applicable to both single-ended and differential lines. As noise margins shrink and it gets harder to reduce other items in the noise budget, such as switching noise, rail collapse and ground bounce, designers will be looking at the low-hanging fruit to squeeze out the last millivolt of noise. One of the places they will be looking is to tighter control on the Zo of the fabricated boards.

Keeping the impedance of all the traces on a board within the specified tolerance is one part of signal integrity noise management. The better that designers understand the sources of Zo variation, the better they can optimize the layout design and stackup to achieve tighter control and bring signal integrity noise within budget.

Accurate Characteristic Impedance

In the manufacturing process, four issues determine whether all traces on all boards fall within the specified impedance range:

1. Choosing the correct dielectric material to meet customer needs and requirements.

2. Choosing the right nominal conditions to hit the target value.

3. Accurate verification of the as-manufactured impedance.

4. Manufacturing variations of each parameter that affects Zo.

In a controlled processing line, predictability is the key to yield, throughput, multiple product capabilities and continued success. Although a number of approximations are available in the literature recommended by IPC for the calculation of Zo, 2D field solvers are far more accurate and versatile, and the latest generation of tools is nearly as easy to use as spreadsheets. The accuracy of some 2D field solvers has been reported to be better than 1% absolute error. (1)

With an accurate predictive tool, it is possible to achieve a target value within 1%. An example of the distribution of measured and predicted impedance values for a variety of cross-sections is shown in FIGURE 2. The average value of the accuracy across all the samples was 0.9%. Any more uncertainty will begin to affect tolerance control.

[FIGURE 2 OMITTED]

Hand-in-hand with the error in predictability is the error in measuring the final Zo. Performing reproducibility studies where traces are measured repeatedly by multiple operators over multiple periods of time show that the variation in the measured values of Zo can vary by more than [+ or -] 2%. Though operator training and improved cables and probes may this value, robotic TDR testing has already demonstrated repeatability of better than [+ or -] 0.1%. (2)

With a reduction in measurement error, the ability to maintain a tighter tolerance is achieved without a reduction in process variations. A separate issue is how well a measurement on a coupon reflects the as-manufactured impedance of a signal trace in the product region of the board. The coupon measurement is typically a few ohms less than the board trace impedances due to proximity and via effects. It is the responsibility of the designer and layout engineer to watch for and design out other causes of impedance variation due to proximity effects of adjacent lines and impedance discontinuities from vias, connectors, pads, reduced plane webs in via fields and packages.

Even if accurate nominal values are established for each design parameter that will affect characteristic impedance, their natural variation in the manufacturing process will affect the variation of Zo.

In general, there are 10 important terms that affect the variation in the as-fabricated impedance.

In general:

1. Dielectric thickness.

2. Dielectric constant (Dk).

3. Line width.

4. Trace thickness.

5. Top-to-foot trace width difference.

For surface traces:

6. Soldermask thickness.

7. Soldermask Dk.

8. Copper height.

For differential pairs:

9. Edge-to-edge separation.

10. Dk of the material between the traces.

With an accurate 2D field solver tool and the nominal values of each of these parameters, the characteristic impedance can be predicted. Using the field solver, the sensitivity of the characteristic impedance to each parameter can be established. Given their normal manufacturing variation, their relative impact to the variation in Zo can be evaluated.

TABLE 1 lists the nominal values, typical percent variation and their contribution to the variation in impedance. This is applicable to a well-controlled manufacturing line. Obviously, the exact values depend on the specifics of the board. For example, if the line width can be kept to [+ or -] 0.0005", this is a 10% variation for a 0.005"-wide line, but only a 5% variation for a 0.010"-wide line.

From this list, it's clear that the most important term is line width control for fine lines, followed by the variation in dielectric thickness and Dk.

A PCB is fabricated from two parts: cores and prepregs. A core is a fully cured glass/resin layer, with a typical thickness of 0.003" to 0.012" and copper clad on both sides. The copper is patterned using standard print-and-etch techniques.

Prepreg is a layer of partially cured resin and glass weave. Single ply prepreg layers come in nominal thickness of 0.0023" to 0.0084". They are composed of one layer of glass weave embedded in a resin. A desired thickness is made up of combinations of one or more prepregs. Between every core is a prepreg layer, and the outer two layers of the stack are typically prepregs with laminated copper foil.

This stack is heated under pressure in the lamination process. The resin in the prepreg flows to fill in all gaps between the copper traces and then cures, acting as the glue to bind the core layers. The end result is a rigid, fiberglass board.

The dielectric spacing between the signal trace and the adjacent reference plane in a microstrip, or planes in a stripline, depends upon the composition of glass and resin content, stackup and lamination conditions.

A core layer can have the most predictable Dk and thickness, as it will not change through processing. Using cores between the signal and adjacent planes will keep the variation in impedance lower. A single layer prepreg will have the smallest variation in dielectric thickness and should be the preferred layer to use. The more glass layers in the prepreg, the more variation there might be due to resin flow during the lamination process.

The Dk of resin in FR-4 is about 3.5. The Dk of the glass weave is about 6. The Dk of the core materials is very stable. Once measured, the variation is less than [+ or -] 5%.

However, the Dk of prepreg will vary depending on the glass/resin ratio, the copper trace density of the adjacent layers, the flow conditions, the orientation of the signals to the glass weave, and the final degree of cure. For tighter control, the properties of the finished prepreg layers must be known.

For differential pairs, the gap between the adjacent signal traces will be all resin from the prepreg flow at lamination. This is shown in FIGURE 3. The predictability of this will affect the differential impedance, especially for very tightly coupled pairs.

[FIGURE 3 OMITTED]

For surface traces, the presence of soldermask acts as another dielectric above the trace and will decrease the characteristic impedance between 5% and 20% depending on line width. An example of the soldermask layer is shown in FIGURE 4. The impact on Zo can be predicted and the line width can be compensated if the nominal thickness and Dk of the soldermask is known. Uncertainty in the parameter values and the accuracy of the calculation will affect the tolerance in Zo.

[FIGURE 4 OMITTED]

From this analysis, the source of the variation in all these terms can be identified and steps established to reduce their variation. The typical variation in as-measured Zo for a buried layer in a multiplayer board with 0.005"-wide traces is shown as a histogram in FIGURE 5.

[FIGURE 5 OMITTED]

In the next few years, standard Zo is expected to migrate to [+ or -] 7% and then [+ or -] 5%. Achieving this goal will require important changes in the way boards are designed and fabricated. Some of the needed changes are:

1. Widescale use of 2D field solvers for accurate predictability of Zo and for sensitivity analysis.

2. Tighter control on the measurement uncertainty using automated robotic testing.

3. More accurate measurements on the dielectric constant of the resin, glass weave, prepregs, cores and solder-masks.

4. Better predictability of the final flow performance of the resin in the prepreg layers, combined with the copper patterns.

5. Tighter line width control and better conductor shape control.
TABLE 1. Sensitivity Analysis Chart

PARAMETER NOMINAL 3[sigma] 3[sigma]
 VALUE VARIATION ZO

Line width 0.005" 10% 2.5[OMEGA]
Dielectric thickness 0.005" 10% 1.5[OMEGA]
Dk 0.0045" 5% 0.75[OMEGA]
Soldermask thickness 0.0004" 10% 0.5[OMEGA]
Trace thickness 0.0012" 20% 0.5[OMEGA]
Copper height of surface traces 0.0022" 30% 0.5[OMEGA]
Dk of material between the traces 0.0035" 10% 0.5[OMEGA]
Top to foot width difference 0.0008" 10% 0.2[OMEGA]
Soldermask Dk 0.0044" 10% 0.2[OMEGA]
Edge-to-edge separation 0.015" 5% 0.1[OMEGA]

Based on characteristic impedance for 0.005"-wide traces in stripline
and microstrip. Note: The variations in impedance typically add as
RMS. Not all these terms would apply to the same specific line.


REFERENCES

1. E. Bogatin, M. Justice,T. DeRigo, S. Zimmer, "Field Solvers and PCB Stack Up Analysis: Comparing Measurements and Modeling" IPC Printed Circuits Expo Proceedings, April 1998.

2. Butler, Brian, "Automated System for Controlled Impedance Testing" CircuiTree, April, 2002.

DR. ERIC BOGATIN is CTO of Synergetix (synergetix.com). He can be reached at eric@ericbogatin.com. STEVE ZIMMER is a quality engineer at Coretec Inc. He can be reached at szimmer@coretec-inc.com.
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Title Annotation:Impedance Control
Author:Zimmer, Steve
Publication:Printed Circuit Design & Manufacture
Date:Apr 1, 2004
Words:2025
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