Achieving high efficiency with power switches.
Load resonant techniques use a resonant feature of capacitors and inductors during the whole switching period, which causes the switching frequency to vary depending on the input voltage and load current. The changing switching frequency, i.e. pulse frequency modulation (PFM), makes it difficult to design an SMPS that includes input filters. Since there is no output inductor for filtering, the clamped voltage across output-rectifying diodes allows designers to select low-voltage rating diodes. However, the absence of the output inductor burdens the output capacitors when the load current increases so that the load resonant techniques are not suitable for applications with high output current and low output voltage.
On the other hand, the zero voltage transition techniques use a resonant feature between parasitic components during only the moment of turn-on and/or turn-off transitions in the switches. One advantage of these techniques is to use the parasitic components such as the leakage inductance of the main transformer and the output capacitance of the switches. So there is no need to add more external components to achieve soft switching. In addition, these techniques take pulse width modulation (PWM) up with fixed switching frequency, making them easier to understand, analyze, and design than load resonant techniques.
Due to its simple configuration and zero voltage swithching (ZVS) characteristic, an asymmetric PWM half-bridge converter is one of the most popular topologies using the zero voltage transition technique. In addition, the ripple component of the output current becomes small enough to be handled by an appropriate output capacitor due to an output inductor compared with load resonant topologies such as LLC converters. It is easy to analyze and design and having an output inductor, it is generally used for the applications with high output current and low output voltage, e.g. PC power supplies and servers. To better handle the output current, a synchronous rectifier in the secondary side is widely used since the conduction losses can be obtained as ohmic losses instead of diode losses. It is much easier to implement the driver for the synchronous rectifier for an asymmetric PWM half-bridge converter than an LLC converter. In addition, a current doubler is a popular solution to increase the use of the main transformer when the output current is high. This article describes the general features of the asymmetric PWM half-bridge converters with current doubler and synchronous rectifier.
Advantage of Asymmetric PWM Half-Bridge Converters with Current Doubler and Synchronous Rectifier
For low output voltage and high output current applications, the current double is widely used. Figure 1 illustrates the asymmetric PWM half-bridge converter with the current doubler on the secondary side. The secondary winding is a single-ended configuration while the output inductors are divided into two smaller inductors. To increase the total efficiency, synchronous rectifiers (SR) comprised of MOSFETs with low [R.sub.DS(on)] are used. The current doubler has several advantages compared to the conventional center-tapped configuration. First, the DC component of the magnetizing current is lower than or equal to that of the center-tapped configuration, which makes it possible for the smaller core to be used for the transformer. The amount of the magnetizing current is the same as that of the center-tapped configuration when each output inductor carries half of the load current.
[FIGURE 1 OMITTED]
The amount of the magnetizing current is reduced when the output inductors carry the load current unevenly. Second, the root-mean-square (rms) value of the secondary winding current is smaller than that of the center-tapped configuration, since almost half of the load current flows through the output inductor each. As a result, the low current density for the secondary winding could be used with the same core and the same gauge of wire. Third, the winding itself is easier than the center-tapped configuration. It is notable especially for multi-output applications because of the limitation of the pin number of the bobbin of the transformer. Fourth, the gate signals for SR are obtained easily and effectively from the output inductors. An appropriate gate voltage, such as between 10 V and 20 V, could be easily obtained from the output inductors owing to their sufficient number of turns, while the secondary side number of turns of the transformer is only a few. Additionally, the separated output inductors will reduce the cost burden of the bigger core. Some of these advantages make the current doubler one of the most popular topologies for high output current applications.
Operational Principles of the Proposed Converter
Seeing Figure 2, let's start with Mode 2, a powering mode. Since S1 turns on, [V.sub.in]-[V.sub.Cb] is applied on the primary side of the transformer. The magnetizing current [i.sub.m] increases with the slope of ([V.sub.in]-[V.sub.Cb])/[L.sub.m]. The slope of the current of [L.sub.O1] is determined by subtracting the output voltage from ([V.sub.in]-[V.sub.Cb])/n because SR2 turns off. On the other hand, the current of [L.sub.O2] decreases with the slope of -[V.sub.O]/[L.sub.O2], which is free-wheeling through SR1. While two output inductors share the load current, SR1 carries the whole load current. The secondary winding of the transformer handles only [i.sub.LO1] so that [i.sub.LO1]/n is the reflected current to the primary side of the transformer and it is superimposed on the magnetizing current, which constitutes the primary current [i.sub.pri]. In fact, [V.sub.t2] is slightly lower than the value illustrated in Figure 2 due to the leakage inductance. However, it is ignored in this section to make analysis easy.
[FIGURE 2 OMITTED]
When S1 turns off, Mode 3 begins. As the output capacitance of S2 is discharged, [V.sub.t1] decreases as well. Finally, it becomes zero when the output capacitance voltage of S2 equals [V.sub.Cb]. At this time, the body diode of SR2 turns on since its reverse biased voltage is eliminated. Then both SRs turn on together during this mode. The body diode of S2 turns on after the output capacitance of S2 is wholly discharged and that of S1 is entirely charged. Since both SRs turn on, [i.sub.LO1] and [i.sub.LO2] are free-wheeling with the slope of -[V.sub.O]/[L.sub.O1] and -[V.sub.O]/[L.sub.O1] and [-V.sub.O]/[L.sub.O2], respectively, and [V.sub.t1] and [V.sub.t2] are zero. It causes the primary current's polarity to change rapidly because [V.sub.Cb] is applied only on the leakage inductance. When S2 turns on after the body diode of S2 conducts, the ZVS condition of S2 is achieved. The duration of this mode is obtained as:
[D.sub.loss2] = [I.sub.o]/n x [L.sub.lk]/[DV.sub.in] x [T.sub.s]
Mode 4, another powering mode, starts with the end of commutation between SRs. The applied voltage on the primary side of the transformer is -[V.sub.Cb]. so that the magnetizing current decreases with the slope of -[V.sub.Cb]/[L.sub.m] and the slope of [i.sub.LO2] is ([V.sub.Cb]/n - [V.sub.O])/[L.sub.O2]. The other inductor current is free-wheeling through SR2. As can be seen in Figure 2, the large ripple on each output inductor is cancelled because of the out-of-phase. Therefore, two smaller inductors can be used in the current doubler configurations compared with the center-tapped or bridge rectifying configurations.
When S2 turns off, Mode 1 starts as another regenerating mode. The operating principle of Mode 1 is almost the same as Mode 3 except for a ZVS condition. In Mode 1, [V.sub.t1] becomes zero at the instant when the output capacitance voltage of S1 is equivalent to [V.sub.in]-[V.sub.Cb]. Before this instant, the load current on the output inductor [L.sub.O2] is reflected to the primary side of the transformer and helps the ZVS condition of the switches to be met. On the contrary, the energy stored in the leakage inductance only has to discharge and charge the output capacitance of the switches after this instant. Therefore, the ZVS condition for S1 is harder than S2 since [V.sub.in]-[V.sub.Cb] is higher than [V.sub.Cb], in general. With this exception, the other things can be analyzed in the same way of Mode 3, The duration of Mode 1 is obtained as:
[D.sub.loss1] = [I.sub.o]/n x [L.sub.lk]/(1-D)[V.sub.in] x [T.sub.s]
The detailed output voltage is calculated with Equations (1) and (2) as:
[V.sub.o] = [L.sub.m]/[L.sub.m] + [L.sub.lk] (D(1-D)[V.sub.in]/n - [I.sub.o][L.sub.lk]/[n.sup.2][T.sub.s]) - [V.sub.SR]
where VSR is the voltage across the MOSFET as an SR during powering modes. The DC and ripple components of [i.sub.m] are obtained as follows:
[I.sub.m] = (1-D)[I.sub.LO2]/n - D[I.sub.LO1]/n
[DELTA][i.sub.m] = ([DT.sub.s] - [D.sub.loss1][T.sub.s]) x (1-D)[V.sub.in]/[L.sub.m] + [L.sub.lk]
where [i.sub.LO1] and [i.sub.LO1] are the DC components of the output inductor currents.
 Hong Mao, Songquan Deng, Yangyang wen, and Issa Batarseh, "Unified steady-state model and DC analysis of half-bridge DC/DC converters with current doubler rectifier," APEC '04. Nineteenth Annual IEEE, Vol. 2, 2004, pp. 786-791.
 Yu-Chieh Hung, Fu-San Shyu, Chih Jung Lin, and Yen-Shin Lai, "Design and implementation of symmetrical half-bridge DC/DC converter", The Fifth International Conference on PEDS, 2003. Vol. 1, Nov. 2003 pp. 338-342.
 Panov, Y. and Jovanovic, M.M., "Design and performance evaluation of low-voltage/high-current DC/DC on-board modules," IEEE Transactions on Power Electronics, Vol. 16, Issue 1, Jan. 2001 pp. 26-33.
By Gwan-Bon Koo, Fairchild Semiconductor
Gwan-Bon Koo is a senior engineer at Fairchild Semiconductor. For more information, contact Fairchild Semiconductor, 82 Running Hill Rd., South Portland, ME 04106; (800) 341-0392; www.fairchildsemi.com
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|Title Annotation:||Power ICs|
|Publication:||ECN-Electronic Component News|
|Date:||Mar 1, 2009|
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