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ATE. (Reader's Resource).

Aliasing The most common type of BIST aliasing occurs when two faults have a canceling effect in the signature register.

ATPG Automatic Test Pattern Generation (sometimes Automated Test Program Generation), Tool based approach to test pattern or program development.

At-Speed Scan Form of scan where testing occurs at the rated frequency of operation. Structure and timing performance can both be verified with this kind of scan test.

BIST Built-In Self-Test.

Boundary Scan Generic term for IEEE 1149 1 It is a methodology allowing complete controllability and observability of the boundary (I/O) pins via a standard interface

BSDL Boundary Scan Description Language

Concurrent Test Performing different tests simultaneously

DFT Design For Test The practice of adding logic to integrated circuits to facilitate effective testing.

DMA Direct Memory Access. An architecture direct that allows direct addressability and observability of embedded memories.

DPM The defect level expressed as defective parts per million units.

EDA Electronic Design Automation. The design tools and environment used to develop the logic draw schematics, and insert scan and BIST for a new chip design.

Fault Coverage Quality measure for a test or set of tests, based on the percentage of actually detected faults vs the total number of theoretically detectable faults.

Functional Testing (also known as behavioral testing), IC, board, and system testing strategy that focuses on the expected functionality of the product.

IDDQ Quiescent Supply Current.

LFSR Linear, Feedback Shift Register.

LSSD Level Sensitive Scan Design Type of scan design that uses master/slave latches with different clock phases to isolate each scan node.

MISR Multiple Input Shift Register. LFSRs configured as signature analyzers used on the back end of BIST engines to capture and compress output sequences from a circuit under test.

Parallel Test Testing more than one device simultaneously. By convention, this usually is assumed to be identical tests on identical devices.

PRPG Pseudo Random Pattern Generator, LFSRs sometimes used on the front end of BIST engines to generate pseudorandom patterns.

Site The logical partitioning of tester resources for each device in a parallel test environment.

SOC System on a Chip. Integration of one or more processor cores, embedded memories, peripheral interfaces, and sometimes mixed-signal circuits onto a single chip to form a complete (or nearly complete) system.

SRSG Shift Register Sequence Generator A simple PRPG (single output).

STIL Standard Test Interface Language. Supported as an output format by the ATPGs of most EDA toolsets. Because STIL is richer in capabilities than WGL, the industry trend is toward full STIL support.

Structural Testing IC testing strategy that focuses on detecting manufacturing defects. Unlike functional or behavioral testing, defects are targeted directly.

STUMPS Self-Test Using MISR and Parallel SRSG A common BIST architecture that combines a PRPG (or multiple SRSGs), multiple scan chains, and a MISR.

TAP Test Access Port. It is a four or optionally five-pin port to enable boundary scan.

WGL Waveform Generation Language. De-facto standard for ATPG and vector generation.

WLBI Wafer-Level Burn-In. A manufacturing technique where a particular product is burned in as full wafers to take advantage of massive parallelism and higher temperature acceleration factors.
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Publication:EE-Evaluation Engineering
Date:Dec 1, 2001
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