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 HOLMDEL, N.J., Dec. 6 /PRNewswire/ -- A team of AT&T Bell Laboratories scientists has used conventional silicon-chip manufacturing processes to produce unconventional chips -- experimental, high-speed devices whose critical dimensions are one thousand times smaller than the width of a human hair.
 The devices operate at room temperature and use far less energy than today's chips.
 "We're continually searching for ways to reduce the size and power consumption of silicon chips," said Ran-Hong Yan, who spearheaded the 16-member team that produced the Bell Labs device. "That makes them faster and more portable, a big plus in the emerging world of battery-operated personal telecommunications."
 The Bell Labs 0.1 micron devices work at room temperature because Yan questioned a belief held by many researchers that silicon chips with features that small cannot work unless they are refrigerated.
 "To make transistors work at that design level, normal processing would have required so much doping that the transistors would behave like resistors," Yan said. Doping is the process for implanting silicon with trace amounts of arsenic and boron to make it function as a transistor. "The transistors can be made to work if you reduce the amount of doping. When you do that, however, unwanted current 'leaks' through the transistors and they get hot. That's why previous 0.1 micron chips produced elsewhere had to be kept cool."
 A process patented by Yan and project teammates Kwing Lee and Abbas Ourmazd eliminates current leakage and, as a result, the need to cool the device. Called "vertical doping engineering," the process uses the bulk silicon commonly found in conventional semiconductor manufacturing. It also makes it possible for the devices to operate at record-breaking speeds.
 Compared to the 0.1 micron experimental devices produced by the Bell Labs team, the most advanced manufacturing processes in commercial use can make silicon integrated circuits (ICs) with features down to 0.5 micron. Today's ICs need power supplies that range from 2.7 to 5.0 volts. The Bell Labs devices work with only 1.5 volts.
 "To paraphrase Mark Twain, news about silicon semiconductors' impending demise is highly exaggerated," said Lee. "Our experience with 0.1 micron devices offers strong evidence that industry's well-established investment and experience in silicon manufacturing processes will continue to be useful well into the 21st Century."
 The semiconductor industry's trend toward smaller design rules is already clear. By mid-1995, for example, AT&T Microelectronics and the NEC Corporation plan to manufacture 0.35 micron complementary metal oxide semiconductor (CMOS) chips in volume, the result of a joint development program the companies initiated two years ago.
 On Nov. 15, the two companies entered into another agreement, this time to develop a process to manufacture ICs using the 0.25 micron design rule. Representatives from both companies have said their joint R&D effort should be completed successfully by mid-1995.
 "The work at Bell Labs will let us move farther down the scale," said Yan. "It's even theoretically possible to cut the design rule in half, down to .05 micron."
 The scientists' work is being reported this week at the International Electron Devices Meeting (IEDM) at the Washington Hilton and Towers, Washington, D.C.
 Bell Labs' CMOS devices include functional circuits for frequency dividers, adders, phase-lock loops, analog-to-digital converters, and low voltage memories. The dividers operate at frequencies in excess of 10 gigahertz (GHz); ring-oscillator delays are less than 12 picoseconds (12-trillionths of a second). Circuits of this sort are commonly found in digital signal processors, microprocessors, and communications electronics.
 The vertical doping concept was tested initially on a computer, using Bell Labs computer-aided design (CAD) tools called PADRE and PROPHET. When the first actual device with vertical doping became available for testing a year later, the results coincided perfectly with those that had been predicted by the computer simulation.
 The devices can function at frequencies up to 116 GHz for N-channel MOS and 51 GHz for P-channel. Previous records for cooled 0.1 micron geometries were 90 GHz for N-channel and 23 GHz for P-channel. Optical devices used to test the speed of gallium arsenide (GaAs) chips do not work with these devices because silicon is much less photosensitive than GaAs. The Bell Labs devices are so fast that present-day testing equipment would be inadequate if they were mass produced.
 This project is part of a continuum at Holmdel of research and development in areas such as high-performance silicon semiconductors. As a logical extension of this project, research continues in the 0.1 micron domain. Mindful of the rapidly expanding market for portable electronic devices, scientists are trying to apply the 1.5 volt power requirement for that geometry to larger design rules.
 In addition to Yen, the research team consists of Kwing F. Lee, Duk Y. Jeon, Gen M. Chin, Young 0. Kim, Don M. Tennant, Behzad Razavi, Horng-Dar Lin, Yih-Guei Wey, Eric H. Westerwick, Mark D. Morris, Robert W. Johnson, T. Mark Liu, Maurice Tarsia, Marcio Cerullo, Robert G. Swartz, and Abbas Ourmazd. All except Lin and Tennant are members of the Silicon Electronics Research Laboratory in Holmdel. Lin is with the Information Systems Research Laboratory; Tennant is with the Photonics Research Laboratory.
 The proprietary CAD programs PADRE and PROPHET were developed by Mark Pinto and Connor Rafferty of the Silicon Electronics Research Laboratory.
 All team members are located at Bell Labs' Holmdel facility. -0-
 /CONTACT: Bert Vorchheimer, 908-582-7889, or at home, 908-464-9512; or Robert Ford, 908-582-4765, or at home, 908-464-4422, both of AT&T Bell Laboratories/

CO: AT&T Bell Laboratories ST: New Jersey IN: TLS SU: PDT

SH-PS -- NY004 -- 0601 12/06/93 08:01 EST
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Publication:PR Newswire
Date:Dec 6, 1993

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