ARM's latest offering, the Cortex architecture, comes in three versions: A, R and M, which target specific types of applications. The M Series is appropriate for cost-sensitive applications that employ a deeply embedded processor. This processor executes only Thumb-2 instructions. (The M Series is available now, and the A and R versions will reach the market shortly.)
Connecting Thumb to ARM
The Thumb-2 instruction set combines 16- and 32-bit instructions to improve code density and performance. The earlier 16-bit Thumb instructions implemented a subset of the original 32-bit ARM instruction set. Not all 32-bit operations, though, efficiently transformed into the shorter Thumb instructions. In some cases, software required multiple Thumb instructions to emulate one 32-bit instruction. Optimizing compilers reduced some of this overhead, and programs written with Thumb instructions reduced code density by approximately 30 percent, but typically at the expense of performance.
Thumb-2 defines new 16-bit instructions that improve program control, new 32-bit instructions derived from the original ARM, and new instructions added to the original ARM instruction set. New bit modification instructions, for example, speed network-data processing and I/O operations that require efficient bit-by-bit manipulations. Developers can use the bit-modify instructions to implement semaphores and other real-time control structures.
To validate the performance of the Thumb-2 instruction set, we used the standard Embedded Microprocessor Benchmark Consortium benchmark suite. The average performance of code written with Thumb-2 instruction runs approximately 98 percent of the performance of the same code benchmarked with 32-bit ARM instructions. In many applications, though, Thumb-2 code requires just 75 percent of the memory taken by 32-bit instructions.
Handle Interrupts Rapidly
The Thumb-2 instructions, combined with the M-series architecture provide the benefits of a 32-bit processor to engineers who struggle to add more functions to 8- and 16-bit microcontroller cores. In automotive systems, for example, designers may seek a microcontroller that controls the brake for each wheel, performs road-holding tasks and reports tire-pressure and system-wear information to a central controller.
The need to deal with many sensors and actuators often demands a processor that can efficiently handle frequent interrupt requests. Much like other microcontrollers, the Cortex-M provides a hardware vectored interrupt controller which ensures that interrupts from peripherals receive service as quickly as possible. But the Cortex-M also implements interrupt "tail-chaining," a hardware technique that lets the processor service two consecutive interrupts without restoring, and then immediately re-saves the original processor-context information between the two consecutive interrupt service routines (Figure). Tail chaining cuts interrupts overhead to a maximum of 12 clock cycles. The Thumb-2 instructions also eliminate the need to switch between ARM and Thumb modes to service interrupts or to provide access to all CPU registers.
Unlike other members of the ARM Cortex family, the ARM Cortex-M Series processors support only the Thumb-2 instruction set, a superset of the older Thumb instruction set. Software tools for the ARM Cortex-M processor include the RealView Compiler and RealView Debug. These tools take advantage of the architectural improvements in debug capabilities, such as the single-wire debug port and improved "visibility" of internal system characteristics and settings. Access to internal debugging information occurs through an embedded in-circuit emulator (ICE) macrocell.
More Cores Coming Soon
As noted earlier, ARM will soon introduce Cortex-R and Cortex-A processor cores. The latter will find use in game consoles, media gateways, high-speed network routers and other devices that run operating systems such as Linux and Windows CE that implement memory-management techniques. Because of the type of applications that the Cortex-A processors can address, ARM includes TrustZone technology that enhances system security. In essence, TrustZone comprises a hardware environment that isolates code and secure software that provides both security services and interfaces. A "monitor" within the core switches between secure and non-secure states. When the monitor switches the system to the secure state, the processor gains additional levels of privilege to run trusted code. It can then handle tasks such as authentication, signature manipulation and secure transactions.
The Cortex-R series targets CPU-intensive real-time systems, such as automotive-safety devices and radar-tracking equipment. Each application will call upon high-performance image-processing algorithms that can take advantage of media accelerators and a core pipeline tuned to run a real-time operating system (RTOS). Both the Cortex-R Series and the Cortex-A Series operate with the ARM and Thumb-2 instruction sets, making them backward-compatible with previous ARM processors.
John Cornish serves as vice president of marketing in ARM's Processor Division (Cambridge, UK). He holds a BSc in Electronics and Computer Science from University College London.
For further reading
Sloss, Andrew N., Dominic Symes and Chris Wright, "ARM System Developer's Guide," Morgan Kaufmann Publishers, San Francisco, CA. 2004. (Does not cover Thumb 2 instructions.)
The Web version of this article--at www.ecnmag.com--contains the sidebar, "What Gives ARM Its Appeal?"
by John Cornish, ARM
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|Title Annotation:||Embedded Systems|
|Publication:||ECN-Electronic Component News|
|Date:||Oct 1, 2005|
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