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ALTERA UNVEILS DSP BUILDER VER. 2.0.

Altera Corporation (NASDAQ:ALTR), San Jose, Calif., has unveiled DSP Builder version 2.0, a major enhancement of its DSP design tool that adds support for the high-performance Stratix(TM) device family as well as new hardware verification and intellectual property (IP) integration features. An intuitive design tool that simplifies the development of digital signal processing (DSP) systems targeted for Altera's programmable logic devices (PLDs), Altera's DSP Builder tool allows DSP designers to realize immediately the benefits of programmable logic without having to learn new design flows or programming languages.

The DSP Builder tool provides a seamless design flow in which designers perform algorithmic design and system-level integration in The MathWorks' MATLAB and Simulink software, respectively, then port the design to HDL for use in Altera's Quartus(R) II design software. With DSP Builder, designers can automatically generate pre-verified RTL output files -- including an RTL design and testbench-from the Simulink software.

In addition to supporting the Stratix device family, this new version of DSP Builder includes an interface to the Quartus II design software's SignalTap(R) embedded logic analyzer. With the new interface, DSP designers can probe the internal nodes of the DSP development board from The MathWorks' MATLAB workspace. The new version also gives designers an interface to SOPC Builder, Altera's system generation tool for the development of system-on-a-programmable-chip (SOPC) applications. The SOPC Builder interface allows the user to build systems that incorporate Simulink designs, Altera Nios(R) embedded processors and IP cores.

"Using DSP Builder for our next-generation equalizer and error correction schemes significantly reduced the amount of time required to evaluate and prove the design," said Pinar Ormeci, design engineer at Narad Networks. "We were able to use the MATLAB and Simulink tools together with the logic blocks found in Altera's DSP Builder to design the equalizer as a Simulink model, simulate it in MATLAB, and then convert it to HDL. DSP Builder even provided the option to synthesize and compile the generated VHDL files automatically, providing us with an ideal platform to design, simulate, synthesize, and compile a complex design and immediately test it on a board."

Additional features of DSP Builder version 2.0 include Altera's OpenCore(R) Plus free test drive DSP IP cores and support for black-box components. OpenCore Plus IP cores currently available with DSP Builder version 2.0 include a Viterbi compiler, constellation mapper/demapper, Reed-Solomon compiler, numerically controlled oscillator (NCO), fast Fourier transform (FFT), infinite impulse response (IIR), and symbol interleaver/deinterleaver. These features allow Altera's DSP Builder tool to facilitate a sophisticated system-level integration and enable designers to implement their own customized logic.

"Altera's DSP Builder continues to push the true capabilities of programmable logic for a variety of emerging high-performance DSP applications," said Ken Karnofsky, director of DSP and Communications at The MathWorks. "DSP Builder version 2.0 provides significant benefits to DSP engineers, making it extremely easy for them to use programmable logic for their designs."

"For a growing number of DSP designers, Altera's DSP Builder tool is bridging the gap between system-level design and implementation in programmable logic," said Justin Cowling, Altera's director of intellectual property marketing. "The advanced signal processing features in Stratix devices combined with Altera's library of 50-plus DSP IP cores allows engineers to quickly and easily develop integrated systems to meet the growing demand and time-to-market requirements for complex DSP applications."

About the DSP Builder Software

DSP Builder interfaces the industry-leading system-level design software Simulink from The MathWorks with Altera's Quartus II design software. DSP Builder provides a seamless design flow, allowing DSP engineers to design algorithms in MATLAB, enabling system integration in Simulink and porting to HDL for design in the Quartus II design software. Designers can automatically generate an RTL design and RTL testbench from Simulink for quick timing and simulation. Further easing the DSP engineer's transition to programmable logic, DSP Builder also enables floating-point to fixed-point analysis.

Pricing and Availability

Altera's DSP Builder version 2.0 is available now to customers with a current DSP Builder subscription. Subscription pricing is $1,995 and includes 12 months of software upgrades. The DSP Builder tool is available for download for free 30-day evaluation from Altera's DSP solutions center at http://www.altera.com/dsp . Simulink and MATLAB are available today from The MathWorks at http://www.mathworks.com/ .

About the Quartus II Software

Altera's Quartus II software delivers superior designer productivity and supports system-level designs with features including LogicLock(TM) block-based design methodology, the PowerFit(TM) fitter technology, support for multi-million gate devices, and integration with third-party software. The Quartus II software supports hardware and embedded software workflows, including a C/C++ compiler and debugger, in a fully integrated development environment to support Altera's Excalibur(TM) embedded processor solutions. The Quartus II software supports major operating systems, including Windows 2000, Windows NT, Windows 98, Sun Solaris, HP-UX and now Red Hat Linux version 7.1. For more information about Quartus II software, visit http://www.altera.com/quartus2 .

About Altera

Altera Corporation is the world's pioneer in system-on-a-programmable-chip (SOPC) solutions. Combining programmable logic technology with software tools, intellectual property, and technical services, Altera provides high-value programmable solutions to approximately 14,000 customers worldwide.

For more information, visit http://www.altera.com or call 408-544-6397.
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Comment:ALTERA UNVEILS DSP BUILDER VER. 2.0.
Publication:CAD/CAM Update
Article Type:Product Announcement
Geographic Code:1USA
Date:Aug 1, 2002
Words:873
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