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ALTERA INTRODUCES QUARTUS II VERSION 2.0 DESIGN SOFTWARE.

Altera Corporation has introduced Quartus II design software, with new features that deliver a 15 percent improvement in design performance and a 50 percent reduction in compile times. The Quartus II version 2.0 design software also minimizes time-consuming design verification tasks to help engineers accelerate their system-on-a-programmable-chip (SOPC) designs. These new capabilities apply to all Altera high-density programmable logic devices (PLDs), including the APEX II device family.

"The Quartus II version 2.0 design software represents a major advancement in the capabilities of programmable logic design software," said Tim Southgate, Altera's vice president of software and tools marketing. "With this new version, Altera is delivering industry-leading design performance, compile times, and productivity features to engineers creating complex SOPC designs."

LogicLock Design Flow Increases Performance

The Quartus II version 2.0 design software achieves an average 15 percent performance improvement, and as high as 25 percent, through an enhanced hierarchical LogicLock block-based design methodology. The LogicLock design flow puts complete control of block placement into the hands of the designer, if required, allowing user-assisted floor planning. The LogicLock design flow also maintains system performance during construction of large SOPC designs by allowing designers to optimize and lock in the performance of each design block individually. The Quartus II version 2.0 design software incorporates new LogicLock design flow algorithms that take advantage of block-based design features in future generations of Altera devices.

"The LogicLock feature in the Quartus II design software is a valuable tool for development of large-scale programmable logic designs," said George Powley, principal staff engineer for advanced technologies in Motorola's Global Telecom Solutions Sector. "By using the LogicLock flow with our designs, we have been able to reduce compile times significantly as well as achieve our clock frequency performance targets."

Reduced Compile Times with Fast Fit Option

The new fast fit compile option provides on average a 50 percent compile time benefit over the default compile settings in the Quartus II version 2.0 design software. The fast fit feature accelerates compile times by conserving the effort typically applied to achieve the best performance. The result is fewer iterations of the fitting algorithm during placement and a much faster compile time with a minimal impact on design performance.

"Using the fast fit option, we were able to reduce the compilation time on our APEX 20K400E designs by 50 percent," said Randy Gill, president of Innocor Ltd. "This savings in engineering resources is critical to companies like Innocor that are building next-generation networking test equipment."

Accelerated Network Compilation Performance

Engineers on UNIX-based networks will reap an additional compile time bonus in the Quartus II version 2.0 design software. Sophisticated compression techniques applied to the Quartus II software result in dramatic reductions in the data transferred across networks, yielding up to a 50 percent reduction in compile times compared to the Quartus II version 1.1 design software.

The same compression techniques resulted in a more than 60 percent reduction in the size of the installed software on a UNIX platform. This reduction lowers the overhead associated with managing the Quartus II design software across a corporate network with multiple users.

"Overall, we are very excited about the improvements made to the Quartus II software on the UNIX platforms," said Craig Martin, design engineer in Alcatel's Research & Innovation Group. "The Quartus II design software has been instrumental in implementing Alcatel's intellectual properties into Altera PLDs that will be used in our next-generation optical router design."

New Features Reduce System Level Verification Effort

The Quartus II version 2.0 design software introduces new features to accelerate the verification process, typically the longest stage of an SOPC design flow. In a fraction of the original compile time, the new SignalProbe technology allows users to incrementally route an internal node to an unused pin for analysis while fully preserving the design's original routing, timing, and design files. SignalProbe technology complements the existing SignalTap embedded logic analysis feature.

Furthermore, designers can quickly develop HDL simulation vectors using the HDL test-bench templates included in the new release. The Quartus II version 2.0 design software can also create complete HDL test-benches automatically from the Quartus II simulator waveform files.

The Quartus II version 2.0 design software also supports the design of high-speed I/O by generating design-specific I/O buffer information specification (IBIS) models that can be exported to popular EDA signal integrity tools. The IBIS models are customized based on the I/O standard settings for each pin in the design and simplify analysis in third-party tools.

Product-Term Device Support

The Quartus II version 2.0 design software now supports Altera's MAX 3000A, MAX 7000AE, and MAX7000B product-term devices in addition to APEX 20KE, APEX 20KC, APEX II, ARM-based Excalibur embedded processor solutions, Mercury, FLEX 10KE and ACEX 1K. MAX 3000A and MAX 7000 designers will now have access to all of the powerful productivity features available only in the Quartus II design software.

Pricing and Availability

The Quartus II 2.0 design software supports major operating systems, including Windows 2000, Windows NT, Windows 98, Sun Solaris, and HP-UX. Altera 's software subscription program simplifies the process of obtaining Altera design software by consolidating all software products and maintenance charges into one annual subscription payment. The annual subscription for the Altera design software is $2,000 for a node-locked PC license, which includes full-featured Quartus II and MAX+PLUS II design software, OEM synthesis tools from Exemplar Logic, OEM simulation tools from Model Technology, and 12 months of software upgrades. New or existing customers may obtain a software subscription online on the Altera web site, http://www.altera.com/, or from Altera distributors worldwide.

About Altera

Altera Corporation is a provider of system-on-a-programmable-chip (SOPC) solutions. Combining programmable logic technology with software tools, intellectual property, and technical services, Altera provides high-value programmable solutions to approximately 14,000 customers worldwide.

Altera can be found on the World Wide Web at http://www.altera.com/.

For more information call 408/544-6397.
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Publication:Productivity Software
Article Type:Product Announcement
Date:Mar 1, 2002
Words:997
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