Printer Friendly

ADVISORY/AXYS Design Automation Demonstrates Unique Modeling Solutions for Multicore SoCs At 38th DAC.

News/Assignment Editors

ADVISORY...for Monday-Thursday (June 18-21)

PALO ALTO, Calif.--(BUSINESS WIRE)--June 15, 2001

AXYS Design Automation, Inc., will be attending this year's Design Automation Conference in Las Vegas, Nevada, and demonstrating their suite of advanced products for the development of system-on-chip (SoC) and high-software content electronic products.

 What: Public booth demonstrations of MaxSim(TM), MaxLib(TM)
 and MaxCore(TM)products applied to complex SoC and
 processor designs. Private suite demonstrations of
 customer designs developed with AXYS Design's

 Date: Monday, June 18, 2001, through Thursday, June 21, 2001

 Time: 9:00 a.m. to 6:00 p.m., Monday through Wednesday, by
 appointment only on Thursday.

 Location: Booth number 1039, Suite number 4420.

 Contact: Gabriele Collier, 650/526-1403,

AXYS Design's Demonstrations include:

Demo 1: Heterogeneous multicore SoC simulation of one ARM7TDMI and two CARMEL DSPs of Infineon Technologies in MaxSim(TM)

The demo shows the creation of a multicore simulation model for an SoC with one ARM7TDMI core and two CARMEL DSPs using the new MaxSim(TM) Designer block diagram editor. The DSPs execute an FFT algorithm, while data transfers through shared memories are controlled by the ARM processor. The simulation is fully cycle-accurate using AXYS Design's MaxLib(TM) models for ARM and CARMEL. The ASPEX debugger is attached to the ARM core while the CARMEL cores are debugged with the CrossView debugger from Protel/Tasking. The overall simulation is controlled from the MaxSim Control Center, which also guarantees the proper synchronization of the debuggers.

Demo 2: MaxSim(TM)-based multicore simulation and debug integrated with Mentor Graphics Seamless-CVE

The demonstration shows the integration of a complete processor subsystem consisting of two ARM7TDMI and two OakDSPCore processors of DSP Group embedded into the popular Seamless-CVE co-verification environment. The processors communicate over shared memory and occasionally reach out to the VHDL model of the memory for external accesses. The ASPEX debugger of ARM is used for the debugging of all processors in the system.

Demo 3: Modeling of advanced DLX processor architectures in MaxCore(TM) environment

Using a simple though powerful C-like description language, MaxCore enables the modeling of even complex processor architectures such as superscalar, VLIW or SIMD. The demonstration shows the expressive power of the MaxCore tool and the high speed of generated models on the examples of the machine description of SIMD, superscalar and VLIW processors. In the demonstration MaxCore automatically generates the simulation model, assembler and disassembler. The resulting model is interactively debugged using the MaxCore debugger with the DDD frontend.

About AXYS Design Automation, Inc.

AXYS Design Automation, Inc. is a provider of fast, accurate and integrated processor models and related C/C++ based SoC modeling and simulation solutions for the development of high-software content system-on-chip (SoC) devices. The MaxSim(TM) environment enables fast, cycle-accurate, synchronous simulation of complex SoC designs incorporating multiple processor cores. MaxCore(TM) automatically generates cycle-accurate processor models and software development tools from an architectural description in the C-like LISA language. The use of AXYS Design's solutions in the pre-silicon phase substantially shortens the SoC design cycle by enabling early system integration and embedded software development, thus reducing NRE cost and time to market.

AXYS Design's growing MaxLib(TM) model library includes processors from Conexant Systems (Nasdaq:CNXT), DSP Group (Nasdaq:DSPG), Infineon Technologies (NYSE:IFX)(FSE:IFX) and LSI Logic (NYSE:LSI). AXYS Design also offers cycle-callable/cycle-accurate models of the ARM (LSE:ARM)(Nasdaq:ARMHY) ARM 7 and ARM 9 architectures and MIPS' MIPS32 and MIPS64 cores. For more information, visit the AXYS Design web site at

Note to Editors: MaxSim(TM), MaxCore(TM), MaxLib(TM) and AXYS are trademarks of AXYS Design Automation, Inc.

All other trademarks are the property of their respective owners.
COPYRIGHT 2001 Business Wire
No portion of this article can be reproduced without the express written permission from the copyright holder.
Copyright 2001, Gale Group. All rights reserved. Gale Group is a Thomson Corporation Company.

Article Details
Printer friendly Cite/link Email Feedback
Publication:Business Wire
Date:Jun 15, 2001
Previous Article:S. Restis Reacts Strongly to Report Re Bond of Enterprises Shipholding Corporation.
Next Article:Corporate Profile for Dyax Corporation, dated June 15, 2001.

Related Articles
AXYS appoints Keith Bindloss as VP of Engineering.
AXYS Design Enables Multicore C/C++ Simulation of MIPS-based Systems-on-Chip.
@HDL Attacks Complex SOC Verification With Adaptive Functional Technology.
AXYS Design Expands Technical Advisory Board.
REMINDER/AXYS Design Automation Demonstrates Unique Modeling Solutions for Multicore SoCs At 38th DAC.
STMicroelectronics Adopts AXYS Design's MaxCore Product for Advanced DSP Processor Development.
DSP Group and AXYS Design Boost Pre-Silicon Design and Verification with New TeakLite Model and Multicore Debugging Support.
AXYS Introduces the MaxView Debugger.

Terms of use | Privacy policy | Copyright © 2019 Farlex, Inc. | Feedback | For webmasters