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A unitary view toward analog weighting/amplifying F-[F.sup.-1] cells/F-[F.sup.-1] funkciju lasteliu itaka analoginiams keitikliams ir stiprintuvams.

Introduction

Usually in VLSI design one linearizes each of the basic gain blocks resulting in a fully linear system that could sometimes limit the input signal that has to work in the linear region of all blocks and may also have an increased complexity lowering in this way operating frequencies [1-3].

Nonconventional techniques based on externally linear internally nonlinear (ELIN) designs [1] use simple nonlinearized internal building blocks to obtain an externally linear circuit. These ones enjoy a good bandwidth-linearity compromise at low voltage operation [2, 4-8]. Other interesting mixed techniques use translinear principle and ELIN topologies for linearizing each block and realizing parameter controls or tuneability [4, 9]. In that way the complexity of the circuit does not increase to much and keep the advantages of ELIN systems.

This paper is focused on a method for linearizing and designing components by using ELIN procedures. We refer to weighting or amplifying cells based only on two modules described by reversible functions F and [F.sup.-1]. Not only Current-mode (C-M) specific for ELIN applications but also Voltage-mode (V-M) circuits are considered. The basic are models implemented in both bipolar and CMOS variants operating in exponential or square-root domain. We show that F-[F.sup.-1] models allow some direct evaluations regarding the design requirements for linearity in large signal operation as well as the opportunity to linearly program or control circuit parameters. Two reference parameters were emphasised for that purpose on each set of particular functions. These unitary and general models not only facilitate the automatic analysis and design process but allow also revealing new reconfigurable and controllable circuits for various applications.

The two general basic models of amplifying/weighting circuits based on nonlinear F and [F.sup.-1] building blocks are introduced in the second section of this paper. Sections 3 presents several circuit variants for implementing functions F and [F.sup.-1] and emphasises their reference parameters. Some possible F-[F.sup.-1] connections are given for example. The validity of design and analysis was proved by simulations. Conclusions are drawn in Section 4.

General models for amplifying/weighting cells

Nonlinear functions F and [F.sup.-1]. Consider an invertible continuous generally nonlinear function F: R[right arrow]R and its inverse [F.sup.-1]: R [right arrow] R so that

[MATHEMATICAL EXPRESSION NOT REPRODUCIBLE IN ASCII] (1)

In a general case F() is no distributive with respect to multiplication. Though in our design we also will find some particular cases when

F (kx) = F (k) [cross product] F (x), (2)

where k is a constant and [cross product] is one of the operators x and [+ or -]. In that case function

F(k[F.sup.-1](x)) = F(k) [cross product] x (3)

will be linear and F(k) represents a gain or an offset. Such functions are for example ln, [square root of], [().sup.2] and satisfy (3):

[MATHEMATICAL EXPRESSION NOT REPRODUCIBLE IN ASCII]

In the following F will be applied to voltages and [F.sup.-1] to currents, so that one defines x and y as normalized currents and voltages with respect to some reference magnitudes with units of currents I or voltages V:

[MATHEMATICAL EXPRESSION NOT REPRODUCIBLE IN ASCII] (4)

Generally, i and v may correspond either to single in/out signals or to differences of signals. Reference parameters I and V in (4) are bias signals or other scaling factors with units of currents or voltages.

Models F-[F.sup.-1] and [F.sup.-1]F. Fig. 1 shows two block diagrams corresponding to general models for both voltage-mode (a) and current-mode (b) weighting/amplifying circuits based on F and [F.sup.-1] functions. Input-output signals are denoted with lowercase letters and reference terms with capital letters.

[FIGURE 1 OMITTED]

[MATHEMATICAL EXPRESSION NOT REPRODUCIBLE IN ASCII] (5)

where [I.sub.2] = [I.sub.1] = 1 [??][v.sub.0] = [v.sub.2] / [v.sub.1] [v.sub.1].

[MATHEMATICAL EXPRESSION NOT REPRODUCIBLE IN ASCII] (6)

Because function F in a very general case is nonlinear and F(nx) [not equal to] nF(x), the condition for a linear [V.sub.out]/[V.sub.in] dependence (relations (5)) implies equal current reference factors ([I.sub.1]=[I.sub.2]). For a current-mode model, the requirement for a linear input/output characteristic consists in equality of voltage reference factors ([V.sub.1]=[V.sub.2]) as relations (6) show.

Remarques:

--Requirements (5) and (6) are useful for determining the conditions for keeping the above amplifying structures in a linear domain not only for small signals but also for large signals.

--The ratios [V.sub.2]/[V.sub.1] and [I.sub.2]/[I.sub.1] could be fixed, resulting in a constant gain (weight) of an amplifying or a weighting circuit. If a reference ratio is linear dependent on an external signal, the output is proportional with the product between input and that signal, resulting in a variable gain amplifier or a multiplying cell.

--If F and/or [F.sup.-1] has the property (2) for such types of functions in/out characteristiques are always linear for large signals. Satisfying requirements (5) or (6) could be required in that case by a linear gain control, nulling offset, or other favourable needed characteristiques.

--Certainly the above models and conclusions regarding linearity for large signals are valid only in the definition domain of [F.sup.-1]-F models, depending on particular circuits that implement the needed structures.

Examples of F and [F.sup.-1] building blocks and corresponding amplifying /weighting circuits

In the following we give some examples of simple circuits that implement a function F and its inverse. For each function two reference terms result and they will determine the design parameters and conditions for large signal domain linearity. They also show if options for programmability or gain control exist.

Basic elementary F - [F.sup.-1] cells with single transistors. F and [F.sup.-1] functions implemented with MOS transistors in saturation. MOS n-channel transistor operating in saturation ([v.sub.DS] > [V.sub.GS] - [V.sub.Th] > 0) for large signals is a nonlinear transconductor and can implement both F squaring and [F.sup.-1] square-root functions as Fig. 2 show.

[FIGURE 2 OMITTED]

The notations are [2]:--K=[mu]x[C.sub.ox], where [mu] is the carrier effective mobility; [-C.sub.ox] is the gate oxide capacitance per unit area;- W and L are the width and length of the channel;--[V.sub.Th] is the threshold voltage; -[lambda] is the channel length modulation factor.

Both [F.sup.-1] and F functions in Fig. 2 satisfy (2):

[MATHEMATICAL EXPRESSION NOT REPRODUCIBLE IN ASCII] (7)

As a consequence relations (8) and (9) will define F-[F.sup.-1] models from Fig. 1 and they are linear:

C-M: [i.sub.o] = ([I.sub.2] / [I.sub.1]) [[(V.sub.1]/[V.sub.2]).sup.2] [i.sub.I], (8)

V-M: [v.sup.*.sub.o] = ([V.sub.2] / [V.sub.1] [square root of (I.sub.1)] / [I.sub.2] [v.sup.*.sub.I], (9)

[??] [v.sub.o] = [V.sub.2] / [V.sub.1]) [square root of (I.sub.1)] / [I.sub.2] [v.sub.I] + [V.sub.2] (1-[square root of (I.sub.1)] / [I.sub.2]), (10)

where [MATHEMATICAL EXPRESSION NOT REPRODUCIBLE IN ASCII].

Relations (8) and (10) show that implementing both types of models given in Fig. 1 with simple saturated MOSTs the resulted circuits have linear large signal in/out characteristics. Gain can be programmed only by setting [[beta].sub.1] and [[beta].sub.2] that is by transistor geometries. To have a V-M circuit without the offset that appears in (10) requirement (5) is needed to be accomplished but (9) corresponds in this case to a unity gain amplifier because if [I.sub.1]=[I.sub.2] taking into account that [V.sub.1]=[V.sub.Th1] and [V.sub.2]=[V.sub.Th2] results in [[beta].sub.1] = [[beta].sub.2].

Examples of F - [F.sup.1] voltage amplifiers based on single MOSTs. V-M model from Fig. 1,a in which F and [F.sup.-1] cells are implemented with transistors as in Fig. 2 corresponds to some basic voltage amplifiers [2] [3] shown in Fig. 3.

[FIGURE 3 OMITTED]

[FIGURE 4 OMITTED]

Because relation (10) is valid, the linear output [v.sub.out] in Fig. 3 can be put under the form

[MATHEMATICAL EXPRESSION NOT REPRODUCIBLE IN ASCII] (11)

Some simulations of circuit from Fig. 3 are shown in Fig. 4 as an example. For example if [L.sub.1]=[L.sub.2] and [K.sub.n] = 3,5 [K.sub.p] an inverting unity gain amplifier has [W.sub.2]/[W.sub.1]=3,5. We refer to large signals for the domain in which F is defined, that is for a saturated transistor when [v.sub.out] > [v.sub.I] - [V.sub.Th1]. One can notice in Fig. 4 that this domain corresponds to straight lines and is larger for smaller gains.

Example of current amplifier/mirror. We can use C-M model from Fig. 1, b to connect the above presented [F.sup.-1] and F cells. Current mirrors or amplifiers result and are described by (8). Because always [V.sub.1]=[V.sub.2] = [V.sub.Th] the circuit is linear and gain is the reference ratio [I.sub.2]/[I.sub.I] = [[beta].sub.1]/ [[beta].sub.1] It can not be controlled, only programmed.

B. F and [F.sup.-1] functions implemented by active BJTs. The three terminal npn bipolar junction transistor (BJT) in the active region of operation could implement F exponential and [F.sup.-1] logarithmical building blocks in a similar connection as in Fig. 2.

[MATHEMATICAL EXPRESSION NOT REPRODUCIBLE IN ASCII] (12)

[I.sub.S] is the saturation current, [V.sub.A] is Early voltage, [V.sub.T] thermal voltage. Reference terms I and V are are in both npn and pnp cases independent each other:

I = [I.sub.S]; V = [V.sub.T]. (13)

Similar circuit functions and conclusions could result connecting in the place of MOSTs in Fig. 3 BJTs. In voltage-mode only cascode connections similar to Fig. 3,c are more usual. For a current-mode bipolar circuit condition (6) is always fulfilled ([V.sub.1]=[V.sub.2]=VT) leading to current mirrors and amplifiers that always operate linearly in large signal domain. Current weights are given by the ratio [I.sub.2]/[I.sub.1]=[I.sub.S2]/[I.sub.S1]=[A.sub.2]/[A.sub.1] where [A.sub.1,2] are the base-emitter areas.

Basic elementary cells with differential transistor pairs

CMOS circuits. Function F can be implemented by an NMOS basic differential common source pair as in Fig. 5,a. The inverse function could be implemented as in Fig. 5,b.

[FIGURE 5 OMITTED]

Examples of CMOS amplifiers. If we use the [F.sup.-1]-F model from Fig. 1b, and building blocks F and [F.sup.-1] from Fig. 5 a current-mode fully differential amplifier results as in Fig. 6.

[FIGURE 6 OMITTED]

[FIGURE 7 OMITTED]

Taking into account (6) and (13) requirement [V.sub.1]=[V.sub.2], for a linear operation of a current-mode circuit in large signal domain results in

[MATHEMATICAL EXPRESSION NOT REPRODUCIBLE IN ASCII] (14)

Simulations in Fig. 7, prove the above results. The largest domain for a linear characteristic corresponds to the gain given in (14) which in our example is 3.

In voltage-mode if requirement (5) is fulfilled that is

[I.sub.T1] = [I.sub.T2] = [I.sub.T] we have

[MATHEMATICAL EXPRESSION NOT REPRODUCIBLE IN ASCII] (15)

A V-M circuit for which (15) is valid in the whole definition domain of function F, that is [MATHEMATICAL EXPRESSION NOT REPRODUCIBLE IN ASCII] as stated in Fig. 5, is shown in Fig. 8.

It can be analysed by simulations in Fig. 9.

The result (15) is known for this amplifier mostly for small signals when the term under the square root sign in (15) can be approximated with unity (that is when [v.sub.I] [much greater than] [square root of (2V)]. Now we know directly that because [I.sub.1] = [I.sub.2], that is [I.sub.T1] = [I.sub.T2], the linearity is also valid for values of [V.sub.I] that may be close to [square root of (2V)], that is for large signals.

[FIGURE 8 OMITTED]

[FIGURE 9 OMITTED]

We can conclude that regarding the above analysed types of circuits neither V-M nor C-M CMOS amplifiers based on model from Fig. 1 and differential transistor pair building blocks offers the opportunity to control linearly weights by an external signal. Setting gain in a large linear domain requires a reconfiguration of transistor pairs in correlation with the current mirrors for the tail currents. For similar schematics with BTJs. Current-Mode F-[F.sup.-1] cells benefit from large signal linearity because the requirement [V.sub.1]=[V.sub.2]=[V.sub.T] is always valid. Reference parameters [I.sub.T1] and [I.sub.T2] are independent one of each other therefore in C-M a linear control or tunability of current gain [I.sub.2]/[1.sub.1] = [I.sub.T2]/[I.sub.T1] by tail currents is also possible.

F-[F.sup.-1] cells based on current mirror loaded transconductor

Circuits implemented with MOSFETs. If the output current difference of the differential F transistor pair in Fig. 8(a) is provided by a single output terminal the well known current mirror loaded transconductor [3] results. F and [F.sup.-1] functions are of the same form shown in Fig. 5 and reference factors V and I are those given in (12).

An [F.sup.-1]-F current amplifier implementing model from Fig. 1(b) is shown in Fig. 10.

[FIGURE 10 OMITTED]

[FIGURE 11 OMITTED]

As in previous section there are the same F and [F.sup.-1] transistor pairs requiring in C-M [V.sub.1] = [V.sub.2] resulting in a similar behaviour shown by simulations in Fig. 11. The maximum domain for the linear out/in characteristic results for (14) when the ratio k between p and IT of the cells is 5.

V-M F-[F.sub.-1] amplifier. A possible implementation of V-M model in Fig. l,a is presented in Fig. 12. Simulations in Fig. 13 show a linear behaviour for the case when tail currents are equal because they satisfy the requirement [I.sub.1]=[I.sub.2] for a linear operation in large signal domain. In this case:

[FIGURE 12 OMITTED]

[FIGURE 13 OMITTED]

BJ Transistors. The same type of schematics from Fig. 10 and Fig. 12 can be built with bipolar current-mirror loaded nonlinear transconductors F and nonlinear grounded resistors [F.sup.-1]. A bipolar transconductor implements a hyperbolic tangent function F [3, 9] as relations (16) show and its inverse is a logarithmical function (17)

[MATHEMATICAL EXPRESSION NOT REPRODUCIBLE IN ASCII] (16)

[v.sub.o] / [V.sub.T] = arcth [i.sub.I]/[I.sub.T]. (17)

Reference factors:

V = [V.sub.T]; I = [I.sub.T]. (18)

For implementing models from Fig. 1 based on the above functions, the requirements for a total nonlinearity compensation for V-M and C-M variants are respectively:

--C-M: requirement [V.sub.1]=[V.sub.2] is always accomplished (see (18)) and thus

[i.sub.o] / [i.sub.j] = [I.sub.2] / [I.sub.1] = [I.sub.T2]/ [I.sub.T1] (19)

One can see that gain can be controlled linearly by the tail current or IT2 can include the second control variable permitting a two input signal product. --V-M: [I.sub.1]=[I.sub.2] that is [I.sub.T1]=[I.sub.T2] resulting in a voltage follower

[v.sub.o] / [v.sub.I] = [V.sub.2] / [V.sub.1] = [V.sub.T] / [V.sub.T] = 1. (20)

Push-pull transconductor

Certainly in a particular case functions F and [F.sup.-1] can be linear as for example in a linear design based on pushpull transconductors (inverters). Fig. 14, (a, c) show two such cells connected to implement both models from Fig. 1. Relations defining each of the two cells for the domain where transistors work in the saturation region are:

[MATHEMATICAL EXPRESSION NOT REPRODUCIBLE IN ASCII] (21)

[MATHEMATICAL EXPRESSION NOT REPRODUCIBLE IN ASCII] (22)

Reference factors are:

V = ([v.sub.Thn] - [absolute value of [v.sub.Thp]])/2, (23)

[MATHEMATICAL EXPRESSION NOT REPRODUCIBLE IN ASCII] (24)

It results that the two linear functions are of the form:

[MATHEMATICAL EXPRESSION NOT REPRODUCIBLE IN ASCII] (25)

where [v.sup.*.sub.I] = [v.sub.I] - 1.

[MATHEMATICAL EXPRESSION NOT REPRODUCIBLE IN ASCII] (26)

where [v.sup.*.sub.o] = [v.sub.o] + 1.

[FIGURE 14 OMITTED]

Taking into account (2), (23), (24), (25) and (26) one can directly derive the for Fig. 14:

[i.sub.o] [[beta].sub.2] / [[[beta].sub.1] [i.sub.I], (27)

[MATHEMATICAL EXPRESSION NOT REPRODUCIBLE IN ASCII] (28)

Simulations from Fig. 14(c) and d prove the validity of this analysis. Straight lines in Fig. 14(c) correspond to large signal domain in MOSFET saturated region of operation.

Conclusions

F-[F.sup.-1] modular structures can cover a large variety of simple weighting/ amplifying circuit implementations. The two reference parameters permit a rapid and direct evaluation of possible ways to program or control such circuits and to extend dynamic range by operating linearly in large signal domains. This principle can be used for many other possible functions to find out new circuit configurations and analyse their behaviour in large signal domain.

Acknowledgement

The authors wish to thank CNCSIS (National Council for Research and High Education) for the financial support (grant no. 657/2009) and Mentor Graphics for their support in the current research.

Received 2010 08 09

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[6.] Festila L., Groza R., Cirlugea M., Fazakas A. Modular analysis and design of log-domain circuits based on LINELIN transformations // Analog Integrated Circuits and Signal Processing.-US: Springer, 2007.-Vol. 50.-No. 3.-P. 231-249.

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[8.] Popa C. Improved Performances Linearization Technique for CMOS Differential Structure // Instrumentation and Measurement Technology Conference Proceedings, IMTC 2007.--Warsaw, Poland, 2007.-P. 1-4.

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L. Festila, L. Szolga, S. Hintea, M. Cirlugea Department of Bases of Electronics, The Faculty of Electronics, Telecommunications and Information Technology, Str. George Baritiu nr. 26-28, Room 55, 400027 Cluj-Napoca, Romania, phone: +(40)-264-401463, e-mail lelia.festila@bel.utcluj.ro
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Title Annotation:ELECTRICAL ENGINEERING/ELEKTROS INZINERIJA
Author:Festila, L.; Szolga, L.; Hintea, S.; Cirlugea, M.
Publication:Elektronika ir Elektrotechnika
Article Type:Report
Geographic Code:4EXRO
Date:Dec 1, 2010
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