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A readout circuit for infrared focal plane array using cascode technique.


A high-performance readout circuit for infrared detectors has a number of requirements, such as high injection efficiency, high dynamic range, high charge storage capacity, low noise, low power dissipation, and small circuit area (Li, T., 2009; Liang, X., 2007). Earlier readout structures, including Self-Integration (SI), Source- Follower-Per-Detector (SFD), and Direct-Injection (DI), are simple and occupy small area, but they cannot satisfy most of the high performance requirements (Li, T., 2009). Later amplifier structures, such as Buffered-Direct-Injection (BDI),Capacitive Feedback Transimpedance Amplifier (CTIA), Buffered Gate Modulation Input (BGMI), and Switched Current Integration (SCI), provide a better performance in terms of injection efficiency and detector bias stability with the help of an inpixel opamp (Liang, X., 2007; Chen, Z., 2008; Fossum, E. and B. Pain, 1993, Hsieh, C.C., 1997), but these performances are limited by the quality of the opamp that should be implemented in a Small pixel area. In addition, CTIA requires an in-pixel integration capacitor (Cint), limiting charge storage capacitance and dynamic range. In summary, all previous circuits have either low performances with simple structures, or high performances with large pixel area, due to their need for an inpixel amplifier and/or an in-pixel capacitor. We have reported a structure which provides high performance without needing an in-pixel opamp or integration capacitor (Hsieh, C.C., 1994; Yoon, N., 1999).

II. Current Mirroring and Cascode:


Figure 1 shows the structure of the designed circuit which is optimized for Ptsi detectors. The detector current is copied linearly and accurately to an off-pixel integration capacitor by the help of a current feedback structure implemented with a NMOS current mirror and a PMOS cascode current mirror. The current feedback structure forces the drain currents of MNl and MN2 to be similar, after mirroring, current goes throw MN3 to cascode structure that can be a amplifier by changing the W/L of MP4 and MP3.the transistors MN3 and MN4 are the bias circuit for cascode structure. The integration capacitor can be placed outside of the pixel; its value can be selected as large as required for high charge storage capacity and high dynamic range.

MNd is a Current-Mode Background Suppression (CBS) circuit that lead overflow current from cascode current mirror to ground to suppress over charge of integration capacitor. Vbias3 tunning the omitted current separated from cascode current mirror the CBS circuit is necessary for infrared detectors to delete bright lights in a dark back ground. Mrsel and Mcsel are selection transistors in an infrared focal plane arrays (IRFPA's), the simulation readout speed can reach 53KHZ with a 6.8pF off-pixel integration capacitor. It is clear that with a smaller integration capacitor higher speeds will be achieved, for a 1pF integration capacitor 2MHZ speed reached. Vbias2 is the cacode circuit bias and Vbias1 is bias voltage to ensure that MN3 and MN4 be in saturated region. Figure 2 shows the selection process to achieve every pixel of a detector array one by one, however if a higher scan rate needed, every row or column should have a decoded address in row or column decoder.



This structure provides a stable bias voltage for the Ptsi detector, which is quite important, since it directly affects the performance and noise of the Ptsi detectors. The feedback structure of current mirror circuit forces the source currents, and therefore, the drain voltages of MN1 and MN2 to be the same (with connivance of second-order effects), providing an accurate and stable bias voltage across the detector. This bias voltage can be set in a large voltage range, limited by the power consumption of circuit and the break down voltage of drain-source. Changes on detector bias of a similar feedback structure are calculated in (Hshieh, C.C., 1998; Hsieh, C.C., 1994; Yoon, N., 1999) as in Equation1:

[DELTA]DET = (Kp / Kn) x [DELTA]VTP + [DELTA] (1)

Where Kp and Kn are geometry constants, and _VTP and _VTN, are threshold voltage mismatches of PMOS and NMOS transistors, respectively. If we import second-order effects, the detector current won't be copied linearly, this is because of difference between VDSMN1 and VDSMN2 .since the transistors in the unit cell are very close to each other, it is possible to draw the transistors such that the mismatch between the pairs will be quite low. As this is valid for all of the pixels in the array, we can achieve a stable detector bias across the array.

The feedback structure also provides very low input impedance, increasing the injection efficiency, i.e. most of the detector current is fed to the readout circuit even for low impedance detectors (Hewitt, M.J., 1994). The input impedance of the designed structures is given as (Yoon, N., 1997).

[] = 1 / [g.sub.m][parallel][r.sub.DS][approximately equal to] 1 / [g.sub.m] (2)

where, Rin is ratio of the change in input voltage due to the change in input current, and the gm values are the transconductance of the transistors and rDS is the impedance of drain-source. Equation 2 suggests that low input impedance can be obtained at low currents of detectors. Detailed simulations show that input impedance can be decreased down to 2 KH for 30 nA detector current with proper design. The output offset voltage is - 4mv that can be deleted in image processor with software. Figure 3 shows a detailed view of the readout channel, which includes a dark current cancellation circuit, switched-capacitor integrator, and sample-and-hold circuit. The dark current in Ptsi detectors can be multiples of the photo current especially temperatures at higher than 77 [degrees]K , so the dark current cancellation circuit is added before the integration stage to increase the dynamic range of the readout channel. This circuit can sink a wide range of dark current, resulting in the integration of the photo current only. Considering the dark current variations due to process mismatches over the detector array, two different dark current cancellation circuits are used, one for course adjustment and one for fine adjustment. The course adjustment is used to subtract the dark current floor, which can be in the orders of a few hundred nano ampers. On the other hand, the fine adjustment is used to subtract column specific small currents, which also helps for non-uniformity correction of variations coming from the detector array, readout array, and readout channels. The integrator in the readout channel converts the buffered detector current to a voltage level and limits the bandwidth of the structure depending on the integration time. It is also possible to change the gain of the integrator by changing the integration capacitances, which is used to adjust the contrast of the image even under very low or very high illuminations. Integration capacitors are reset at times in order to make the circuit ready for the next column.

III. Simulation Results:

Figure 4 shows the simulated integration curves for different detector currents, where the detector current is buffered by current mirror and cascode structure. As seen in the figure, a voltage swing near to 1.8V is achieved with a 6.8pF off-pixel integration capacitance used in the designed circuit.

The linear working range of designed circuit is from 1nA to 200nA of ptsi detectors output with a 6.8pF off-pixel integration capacitor. Minimum detectable current of designed circuit is 1nA that allow detecting very dark places. To have a picture with high quality that scanned with ptsi matrix detectors, the detector output should be included a wide range of currents, this subject force the detector circuits working in a wide range of detectors current linearly. The designed structure enables the use of off-pixel integrator capacitance without loss in linearity. The maximum charge storage capacity of the system is 76.5x106 electrons with 1.8V output voltage swing, which enables the use of longer integration times with the loose of frame rate. It should be noted that, when long integration time in the orders of milliseconds is required, an in-pixel capacitor can also be used as the designed circuit occupies a small area in the pixel. The integrator is followed by Sample and Hold Circuit (S/H), which is optimized for least noise contribution in terms of clock feed through (Yoon, N., 1997). Figure 5 shows the temperature range for a good service of this circuit. The temperature should be at the range of -150 [degrees]c up to- 80 [degrees]c , (123[degrees]K up to 193[degrees]K); this is a proper temperature for most ptsi detectors.



The output offset voltage is -4mv that can be deleted with software in image processor. Simulation results shows that by 5nA changing at detector current, the voltage in integration capacitor changes 300mV, at detector low current range, shows that Amplifying of the designed circuit decreasing at higher currents of detectors and implying a feedback to create a semi flat light amplitude histogram (Kulah, H. and T. Akin, 1998; Kulah, H. and T. Akin, 2003). This feature also shows that the designed circuit has good detachment and amplification for detector low currents that created at dark places. The power dissipation

for each cell is 750nW and mostly used with the power supply, Vdd. Changing at integration capacitor shows that designed circuit has high swing output for small capacitors and by using large capacitors the reset pulse ,that discharge integration capacitor ,should be at longer time and scan rate will be decreased. Figure 6 shows the simulated output of the circuit for different integration capacitors of 1pF, 3pF, 5pF, 7pF and 9pF while the detector current is 30nA.

Using small integration capacitor cause faster scan rate while a better dynamic range achieves at big integration capacitors. MOS IC processes have both a major and a minor statistical distribution of manufacturing tolerance parameters. The major distribution is the wafer-to-wafer and run-to-run variation. The minor distribution is the transistor-to transistor process variation. The major distribution determines electrical yield. The minor distribution is responsible for critical second-order effects, such as amplifier offset voltage and flip-flop preference. Figure 7 shows the monte carlo analyse on designed circuit with Gaussian distribution and 27% distribution in the variation of the channel lengths and the parameter that controls the difference between the physical gate length and drawn gate length, PHOTO parameter, at the [+ or -]3-sigma level.

The results shows for 10 simulation, 7 output is acceptable. It means that the designed circuit is 70% immune from changing on length of transistors ,since the simulations are at 30nA detector current and 6.8pF off-pixel integration capacitor.


IV. Conclusion:

This paper reports the simulation of a readout circuit which is based on current mirroring integration and cascode technique that optimized for Ptsi detectors. The designed circuit provides almost 100% injection efficiency, very low input impedance, while occupying small area (with 11 transistors). The circuit simulated at 0.18Jm CMOS process. Simulated results show that the non-linearity of the circuit is smaller than 4 LSB for 10bit resolution. The speed reached 53KHZ with a 6.8pF off-pixel integration capacitor The simulated results also show that the designed circuit has a very good potential for high performance IR FPA applications.




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Houshyarifar, Vahid

Islamic Azad University, Urmia Branch, Urmia, Iran.

Vahid Houshyarifar; A Readout Circuit for Infrared Focal Plane Array Using Cascode Technique

Corresponding Author: Vahid houshyarifar, Islamic Azad University, Urmia Branch, Urmia, Iran.

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Title Annotation:Original Article
Publication:Advances in Natural and Applied Sciences
Article Type:Report
Geographic Code:7IRAN
Date:Jul 1, 2011
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