A novel approach to induction motor speed control using FPGA.
In recent years there has been a great demand in Industry for adjustable speed drives. Induction motor is used in many Industrial applications such as HVAC (heating, Ventilation and air-conditioning) Industrial drives (motion control, robotics), Automotive control (electric Vehicles) etc. However, Induction motors can only run at their rated speed when they are connected to the main power supply. This is the reason why variable frequency drives are needed to vary the rotor speed of an induction motor. The most popular algorithm for the control of a three phase Induction motor is the V/F control approach using a natural pulse width modulation (PWM) technique , ,  to a drive a voltage source Inverter (VSI). The aim of this paper is to show how these techniques can be easily implemented in Xilinx XC3S 400E FPGA based controller dedicated to power control application.
Induction Motor with Constant Flux
The constant volts per hertz's principle is today the must common control principle need in adjustable speed drives of Induction machines. The synchronous speed is directly proportional to the supply frequency. Hence, the synchronous speed and the motor speed can be controlled below and above the normal full-load speed by changing the supply frequency. The voltage induced in the stator E is proportional to the product of the supply frequency and the air-gap flux. If the stator drop is neglected the motor terminal voltage can be considered proportional to the product of the frequency and the flux. Any reduction in the supply frequency, without a change in the terminal voltage, causes an increase in the air-gap flux. 
Induction motors are designed to operate at the knee point of the magnetization characteristic to make full use of the magnetic material. Therefore, the increase in flux will saturate the motor. This will increase the magnetizing current, distort the line current and voltage, increase the core loss and the stator copper loss, and produce a high-pitch acoustic noise. While an increase in flux beyond the rated value is undesirable from the consideration of saturation effects, a decrease in flux is also avoided to retain the torque capability of the motor. Therefore, the variable frequency control below the rated frequency is generally carried out by reducing the machine phase voltage V along with the frequency F in such a manner that the flux is maintained constant. , . Above the rated frequency, the motor is operated at a constant voltage because of the limitation imposed by the stator insulation or by supply voltage limitations.
The operation of the machine at a constant flux requires a closed-loop control of flux. When the operating point changes, the closed-loop control adjusts the motor voltage to maintain a constant flux. The closed-loop control becomes complicated because the measurement of flux is always difficult. Hence the flux is controlled indirectly by operating the machine at a constant (V/F) ratio for most of the frequency range, except at low frequencies.  There is a large increase in the starting and low-speed torques with variable frequency control. The corresponding currents are also reduced by a large amount. Thus the starting and low-speed performance of variable frequency drive is far superior compared to that with the fixed frequency operation.
Implementation of FPGA Controller
A Field programmable Gate Array is digital integrated circuits that can be programmed to do any type of digital function. There are two main advantages of an FPGA over a Microprocessor chip for controller:
1. An FPGA has the ability to operate faster than a microprocessor chip.
2. The new FPGAs that are on the market will support hardware that is upwards of One million gates. The FPGA consists of three major configurable elements which is shown in Figure 1:
1. Configurable Logic Blocks (CLBs) arranged in an array that provides the Functional elements and implements most of the logic in an FPGA.
2. Input-output blocks (IOBs) that provide the interface between the package pins and internal signal lines.
3. Programmable interconnect resources that provide routing path to connect inputs and outputs of CLBs and IOBs onto the appropriate network.
[FIGURE 1 OMITTED]
The real time control system is implemented using FPGA XC3 400E from Xilinx, Inc. The block diagram of the controller is shown in figure 2.
[FIGURE 2 OMITTED]
The controller contains
1. 16 x 2 LCD display
2. PLL oscillator.
3. Clock source selector.
4. Xilinx SPARTAN 3 FPGA1
5. JTAG connecter for FPGA1
6. XCF02S Flash PROM
7. 26 Pin I/O Termination
8. 16 Nos of LED
9. 34 Pin I/O Termination
10. Level Translators
11. Xilinx SPARTAN 3 FPGA 2
12. 4Nos of ADC (AD 7266)
13. JTAG connecter for FPGA2
14. 4 x 2 micro switches
15. AD 5328 (DAC)
The Xilinx ISE Foundation computer-aided-design tool is used for the design and development of the FPGA.  The FPGA design flow for the system is given as follows: First, the system is implemented using the Xilinx ISE foundation tools and simulated at the register transfer level to verify the correctness of the design. By using the Xilinx ISE Foundation tools, the logic synthesis is carried out to optimize the design, and the placement and routing are carried out automatically to generate the FPGA implementation file. , .
Finally, the generated implementation file is downloaded to the FPGA development board for testing.
This paper is intensifies three phase Induction motor drive based FPGA controller. Constant flux technique (V/F) is used for induction motor speed control. For test of proposed FPGA controller performance, driver is implemented.
Block diagram of implemented circuit
The block diagram of Implemented drive is shown in figure 3.
[FIGURE 3 OMITTED]
The block diagram consists of FPGA Controller, Quadrature Encoder Pulse, A/D Card, Intelligent Power Module, and 1HP Induction Motor.
Intelligent power module with the specification of 1200V, 25A IGBT as the switching devices is being used in the experiment. Current and Voltage are sensed by using Hall Effect principle. Speed of the Induction motor is sensed by Quadrature Encoder pulse (QEP). The output of speed sensed is feed to frequency to voltage converter circuit. In this module set the frequency to voltage converter with maximum output of 2.5V at rated motor speed of 1500rpm.
Speed error is calculated with comparison between the set speed and process speed from feedback. Speed error is given as Input to FPGA XC3S400E Controller. FPGA controller gives gate drive signal to intelligent power module there by stabilizing the speed of the Induction Motor using constant flux principle.
Proportional-Integral (PI) Controller
A controller produces an output signal consisting of two terms, one proportional to the actuating signal and the other proportional to its integral. Such a controller is called a Proportional Integral Controller (PI) and is shown in Figure. 4
[FIGURE 4 OMITTED]
The control action of PI controller is defined by the following equation (4.1) U(t)=Kc [e(t)+1/Ti [integral] e(t) dt (4.1)
The proportional control action multiplies the error signal by a constant to improve the overall gain of the system. If the proportional control is employed, a steady state error is necessary to have a steady output. If an integral control replaces a proportional control, steady state error can be made to zero but induction of an integral controller into the closed loop will create instability or at least poor dynamic behavior. Derivative control improves the dynamics of the system response. It provides an anticipatory action to reduce the overshoots in the system response. The proportional-integral and derivative control actions can be combined to give an effective control action.
Certain specifications are to be considered for the design of the PI controller with respect to the closed loop response of the compensated system to the unit step input.
These specifications are chosen as:
1. Overshoot should be less than 5%
2. Settling time should be less than 3 seconds.
First keeping the value(s) of [K.sub.I] = 16.5 as constant, [K.sub.P] is tuned till the over shoot is reduced.
Next the value(s) of [K.sub.P] = 0.5 is kept constant, [K.sub.I] is tuned till the settling time is reached.
Evaluation and Experimental Results
In Figure 5 shown a Experimental setup diagram
[FIGURE 5 OMITTED]
In Experimental test, sudden change has exerted in motor process speed. Speed command changes in two cases: No load and Full load with increasing and decreasing speed command in open loop and closed loop.
Driver responses are depicted in Figure (6) for No load case in open loop. Figures (6-a) and (6-b) show driver responses. In suddenly increasing speed, first, motor command speed to 500 rpm, Reference speed is changed to 700 rpm at t=1 sec, but in decreasing speed, primary motor speed is 700 rpm, which is decreased to 500rpm at t=1 sec, rise time in each case is nearly 0.1 sec, also there are no overshoot in responses and steady state error is dispensable. In these tests, speed regulation is almost suitable.
[FIGURE 6a OMITTED]
[FIGURE 6b OMITTED]
[FIGURE 7a OMITTED]
Figure 7 Depicts driver response to sudden speed change in No load and Full load case, in closed loop condition. Driver responses are shown in figures (7-a), (7- b), (7-c), and (7-d) for increasing and decreasing reference speed respectively. In these tests, reference speed changing is exerted at t=1 sec, steady state error is almost 5%. In each condition, driver rise time is less than 0.1 sec. Driver response depicts no overshoot.
[FIGURE 7b OMITTED]
[FIGURE 7c OMITTED]
[FIGURE 7d OMITTED]
Figure (8) shows After Load Change driver response. In steady state, motor speed is 700 rpm. At t=1 sec, motor load is changed to an amount of 50% of nominal load. In this condition, motor speed decreases, to approximately 24 rpm during 1.15 sec, as can be seen in figure after this time, motor speed returns to primary speed again.
[FIGURE 8 OMITTED]
Synthesis Report of the Controller
All the modules are integrated and synthesized using Xilinx project navigator and support tools. ,  .The synthesized VHDL source code is placed and routed. Finally, a bit file is created. This bit file is fused into the Xilinx XC 3S 400E-4PQ208 FPGA and interfaced with the input and output device. Appendix shows the synthesis report of the controller.
VHDL coding for speed control of Induction motor
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity speed is Port (clock : in std_logic; -- 20 mega hz; swt1 : in std_logic; swt5 : in std_logic; Lcd Control Pins cs : out std_logic; diow : out std_logic; rs : out std_logic; data : out std_logic_vector(7 downto 0); sen_a : in std_logic; RxD_d : in std_logic; TxD_d : out std_logic; pulse1 : out std_logic; pulse2 : out std_logic; pulse3 : out std_logic; pulse4 : out std_logic; pulse5 : out std_logic; pulse6 : out std_logic; oe1 : out std_logic; dir1 : out std_logic; oe6 : out std_logic; dir6 : out std_logic; oe5 : out std_logic; dir5 : out std_logic; oe3 : out std_logic; dir3 : out std_logic); end speed ; architecture struct of speed is component freg_measure is port (clk : in std_logic; ---20 mhz; cls_rpm : in integer; Rpm_in : in integer; chs_prg : in std_logic_vector(7 downto 0); Frequency : out integer; Freqstep : out integer; amplitude : out integer); end component; component pulse6_out is port (clock : in std_logic; ---20 mhz; chs_prg : in std_logic_vector(7 downto 0); freqstep_in : in integer; amplitude_in : in integer; pulse1 : out std_logic; pulse2 : out std_logic; pulse3 : out std_logic; pulse4 : out std_logic; pulse5 : out std_logic; pulse6 : out std_logic); end component; component lcd_sp is Port (clock : in std_logic; -- 20 mega hz; swtch1 : in std_logic; swtch5 : in std_logic; cs : out std_logic; diow : out std_logic; rs : out std_logic; data : out std_logic_vector(7 downto 0); sp_out : out integer; fdbk_rpm : out integer; pv_rpm : in integer; chs_prg : in std_logic_vector(7 downto 0)); end component ; component pi_controll is port(clk : in std_logic; chs_prg : in std_logic_vector(7 downto 0); speed : in integer; fd_bk : in integer; output : out integer); end component; component tx is port (clk : in std_logic; set_pt : in integer; pv : in integer; Frequency : in integer; recv_data : out std_logic_vector(7 downto 0); RxD_d : in std_logic; TxD_d : out std_logic); end component; component QEP is port(clock : in std_logic ; sen_a : in std_logic; rpm : out integer); end component; signal setspeed,sss, amp, freg,pv_con,Freqstep,frq_hz,pv_dsp : integer := 0; signal prg : std_logic_vector(7 downto 0); begin pmap1 : lcd_sp port map (clock, swt1, swt5,cs,diow,rs,data,setspeed,pv_dsp,pv_con,prg); pmap2 : pi_controll port map (clock,prg, setspeed, pv_con, sss); pmap3 : freg_measure port map (clock,sss,setspeed,prg,frq_hz, Freqstep,amp); pmap4 : pulse6_out port map (clock,prg,Freqstep, amp, pulse1, pulse2, pulse3, pulse4, pulse5, pulse6); pmap5 : tx port map (clock,setspeed,pv_dsp,frq_hz,prg,rxd_d,txd_d); pmap6 :qep port map (clock,sen_a,pv_con); oe1 <= '0'; dir1 <= '1'; oe5 <= '0'; dir5 <= '1'; oe3 <= '0'; dir3 <= '0'; oe6 <= '0'; dir6 <= '0'; end struct;
This paper demonstrates that speed control of induction motor system can be controlled using FPGA controller. The control scheme was modeled and designed in VHDL, simulated and synthesized using Xilinx Foundation package and implemented into Xilinx XC3S400 FPGA. Laboratory test of performance of an Induction motor with FPGA controller was implemented. Induction motor drive was implemented with suitable speed regulation.
1. HDL Synthesis Report for the speed control of Induction motor
#ROMs :7 17 x 8-bit ROM :4 256 x 32-bit ROM :3 #Multipliers :12 32 x 12-bit multiplier :1 32 x 14-bit multiplier :2 32 x 16-bit multiplier :2 32 x 17-bit multiplier :3 32 x 6-bit multiplier :1 32 x 7-bit multiplier :1 32 x 9-bit multiplier :1 9 x 13-bit multiplier :1 # Adders/Subtractors :76 11-bit adder :5 11-bit addsub :2 11-bit subtractor :4 12-bit adder :9 12-bit subtractor :3 17-bit adder :3 18-bit adder :4 22-bit adder :1 24-bit adder carry out :1 25-bit adder :1 28-bit adder :1 3-bit adder :1 32-bit adder :17 32-bit subtractor :3 4-bit adder :8 5-bit adder :1 8-bit adder :8 8-bit adder carry out :2 9-bit subtractor :2 # Counters :9 12-bit up counter :4 32-bit up counter :5 # Registers :115 1-bit register :40 11-bit register :8 12-bit register :6 18-bit register :3 22-bit register :1 25-bit register :2 3-bit register :1 32-bit register :23 4-bit register :12 5-bit register :1 8-bit register :18 # Comparators :73 11-bitcomparator greatequal :8 11-bit comparator less :2 12-bit comparator greatequal :3 12-bit comparator greater :8 12-bit comparator less :10 12-bit comparator lessequal :7 18-bit comparator less :3 22-bit comparator greatequal :1 32-bit comparator equal :2 32-bit comparator greatequal :2 32-bit comparator greater :10 32-bit comparator less :5 32-bit comparator lessequal :4 32-bit comparator not equal :2 5-bit comparator less :4 9-bit comparator greater :2 # Multiplexers :9 32-bit 4-to-1 multiplexer :6 8-bit 4-to-1 multiplexer :2 8-bit 8-to-1 multiplexer :1
2. Device utilization summary for the speed control of induction motor Selected Device: 3s400pq208-4
Number of Slices 2438 Out of 3584 68% Number of Slice Flip Flops 1216 Out of 7168 16% Number of 4 input LUTs 4643 Out of 7168 64% Number of Bonded IOBs 31 Out of 141 21% Number of MULTI8X18s 16 Out of 16 100% Number of GCLKs 2 Out of 8 25%
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R. Arulmozhiyal * and K. Basakaran ($)
* Faculty, Sona College of Technology, Salem-636005, TamilNadu, India.
($) Senior Lecturer, Government college of Technology, Coimbatore-13, TamilNadu, India. E-mail: email@example.com, firstname.lastname@example.org
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|Author:||Arulmozhiyal, R.; Basakaran, K.|
|Publication:||International Journal of Applied Engineering Research|
|Date:||Jan 1, 2009|
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