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A novel PWM scheme for multilevel voltage source inverter fed induction motor.

Introduction

The rapid development of the capacity and the switching frequency of power semiconductor devices and the continuous advance of the power electronics technology have made many changes in static power converter systems and industrial motor drive areas. Especially, the voltage source PWM inverters have been extending their application area widely due to the increase of gate turn-off (GTO) thyristors capacity and continuing development of industrial provision [1-4]. Three-level inverter topology being widely used in high voltage/ high power applications due to its high voltage handling and good harmonic rejection capabilities with currently available power devices like GTOS.

Since conventional GTO inverter has a limitation of its DC-link voltage about 2000V, series connection of existing GTO thyristors has been essential in realizing high voltage and large capacity inverter configuration with DC-link voltage about 4000V. So there has been great interest in three-level inverter topology which can over come series connection problems, Three-level inverter is able to generate five-level line-to-line output voltage without output transformer or reactor. Therefore, the harmonic components of the output voltage are fewer than those of the conventional two-level inverter at the same switching frequency [10]. In addition, since the blocking voltage of each switching device is a half of the DC-link voltage, it is easy to realize high voltage and large capacity inverter system.

Space Vector Pwm For Three-Level Inverter

A three-level inverter topology and switching states

Fig.1 shows a schematic diagram of a three-level GTO inverter .Each phase of the inverter consists of two clamping diodes, four GTO s and four free wheeling diodes. Since three kinds of switching states and terminal voltages exist in each phase, the three level inverter has 27([3.sup.3]) switching states. Fig. 2(a) shows the representation of the space voltage vectors for output voltage. According to the magnitude of the voltage vectors, we divide them in to four groups; zero voltage vector (Vo), small voltage vectors ([V.sub.1], [V.sub.4], [V.sub.7], [V.sub.10], [V.sub.13], [V.sub.16]), middle voltage vectors([V.sub.3], [V.sub.6], [V.sub.9], [V.sub.12], [V.sub.15], [V.sub.18]) and large voltage vector ([V.sub.2], [V.sub.5], [V.sub.8], [V.sub.11], [V.sub.14], [V.sub.17]). The zero voltage vector (ZVV) has three switching states, the middle voltage vector (MVV) has two and the large voltage vector (LVV) has one state. Fig. 2.2(b) shows the same representation for Fig. 2.2(a). It shows the space vector diagram of all switching states, where the P, O, N represent terminal voltage respectively, that is Vdc/2, 0, -Vdc/2.

[FIGURE 1 OMITTED]

[FIGURE 2 OMITTED]

B. Voltage Vector and its Duration

Fig. 3 shows the triangle formed by the voltage vectors [V.sub.0], [V.sub.2] and [V.sub.5]. This triangle is divided into four small triangles 1, 2, 3 and 4. In the space voltage vector PWM, generally, output voltage vector is formed by its nearest three vectors in order to minimize the harmonic components of the output voltage and the current. The duration of each vector can be calculated by vector calculation. For instance, if the reference voltage vector falls into the triangle 3, the duration of each voltage vector can be calculated by the following equations.

[V.sub.1][T.sub.a] + [V.sub.3][T.sub.b] + [V.sub.4][T.sub.c] = V * [T.sub.s]

[T.sub.a] + [T.sub.b] + [T.sub.c] = [T.sub.s]

[V.sub.1] = 1/2, [V.sub.3] = [square root of (3)]/2 [e.sup.j[pi]/6], V * = [Ve.sup.j[theta]]

Where Ts = sampling time for reference voltage vector.

The results are as follows:

[T.sub.a] = [T.sub.s] [1-2k sin([theta])]

[T.sub.b] = [T.sub.s] [2k sin([theta]+60)-1]

[T.sub.c] = [T.sub.s] [2k sin([theta]-60)+1]

where k = 2 V/[square root of (3)]

In other regions (1, 2, 4), the duration for each voltage vector can be calculated in the same way.

[FIGURE 3 OMITTED]

Switching Pattern Generation Considering Minimum On/Off Time

[FIGURE 4 OMITTED]

Mathematical Model of Induction Machines

The induction machine is implemented in simulink using the following mathematical model

[v.sub.qa] = [r.sub.s] [i.sub.qs] + [omega][[lambda].sub.ds] + p[[lambda].sub.qs]

[v'.sub.qr] = 0 = [r'.sub.r] [i'.sub.qs] + ([omega] - [[omega].sub.r][[lambda]'.sub.dr] + p[[lambda]'.sub.qr]

[v.sub.ds] = [r.sub.s] [i.sub.ds] - [omega][[lambda].sub.qs] + p[[lambda].sub.ds]

[v'.sub.dr] = 0 = [r'.sub.r] [i'.sub.dr] - ([omega] - [[omega].sub.r][[lambda]'.sub.qr] + p[[lambda]'.sub.dr]

[omega] = angular speed of arbitrary reference frame P = d/dt

Where

[[lambda].sub.qs] = ([1.sub.s] + [L.sub.m])[i.sub.qs] + [L.sub.m][i'.sub.qr] = [L.sub.s][i.sub.qs] + [L.sub.m][i'.sub.qr]

[[lambda]'.sub.qr] = ([1']r + [L.sub.m])[i'.sub.qr] + [L.sub.m][i.sub.qs] = [L'.sub.r][i'.sub.qr] + [L.sub.m][i'.sub.qs]

[[lambda].sub.ds] = ([1.sub.s] + [L.sub.m])[i.sub.ds] + [L.sub.m][i'.sub.dr] = [L.sub.s][i.sub.ds] + [L.sub.m][i'.sub.dr]

[[lambda]'.sub.dr] = ([1']r + [L.sub.m])[i'.sub.dr] + [L.sub.m][i.sub.ds] = [L'.sub.r][i'.sub.dr] + [L.sub.m][i.sub.ds]

Therefore

[MATHEMATICAL EXPRESSION NOT REPRODUCIBLE IN ASCII]

And

Te = [P.sub.m]/[[omega].sub.m] = 3/2 P/2 [L.sub.m]/[L'.sub.r] [[[lambda]'.sub.dr][i.sub.qs] [[lambda]'.sub.qr][i.sub.ds]]

[[omega].sub.m] = [T.sub.e] - [T.sub.L]/[J.sub.s] + B; [[omega].sub.r] = P/2 [[omega].sub.m]

Simulation Results

Simulation was carried out for two level and three level inverter fed induction motor. The parameters of induction motor used for simulation are as follows:

220 V, 50 Hz, 4 pole, 3 HP,

Rs = 0.55 ohms, Ls = 93.38 mH,

Rr = 0.78 ohms, Lr = 93.36 mH, Lm = 90.5 mH,

J = 0.019 Kg-[m.sup.2], B = 0.000051, [T.sub.L] =10.32 N-m

[FIGURE 5 OMITTED]

[FIGURE 6 OMITTED]

A. Simulation Results for 2-level and 3-level SVPWM VSI Fed induction motor

[FIGURE 7 OMITTED]

[FIGURE 7a OMITTED]

[FIGURE 7b OMITTED]

[FIGURE 7c OMITTED]

[FIGURE 7d OMITTED]

[FIGURE 8 OMITTED]

[FIGURE 8a OMITTED]

[FIGURE 8b OMITTED]

[FIGURE 8c OMITTED]

[FIGURE 8d OMITTED]

Conclusion

In this paper, the application of space vector pulse width modulation control strategy on the three level voltage source inverter has been presented and analyzed. The aim of this paper is to prove the effectiveness of the SVPWM for contribution of the switching power losses for reduction, and to show the effectiveness of three level inverters that carry out voltage harmonic reduction than those of the two level inverters. On the other hand from simulation results, it is observed that as modulation index is increased the THD decreases and fundamental RMS value increases linearly. It is observed that the simulation results have been good agreement with the published work.

References

[1] Q. Zeng L. Chang, P. Song, "Space Vector Pulse Width Modulation inverter based Current controller," 35th Annual IEEE Power Electronics Specialists conference, 2004.

[2] T. A. Neynand, H. Foch, "Multilevel conversion: High Voltage Chopper and Voltage Source Inverters," IEEE PESC 1992.

[3] Hyo L. Liu et al., "three level SVPWM in linear index modulation region a voiding narrow pulse problem," IEEE PESC.

[4] Abdul Rehiman Beig, PhD Thesis on "Application of three level Voltage Source Inverter to voltage fed current fed high power induction motor drives," IISC, Bangalore, April 2004.

[5] H. Pinheiro, F. Botteron, C. Rech, L. Schuch, "Space Vector Modulation for Voltage Source Inverter: A unified Approach," Proceedings of the 28th Annual conference of IEEE industrial Electronics society: Vol: 4, 2002.

[6] "A Novel of PWM Schemes for 3-level VSI with GTO's thyristors based on space vector modulation," IEEE IECON Conf: Rec.

[7] Jin-Woo Jung, PhD student, "SVPWM inverter," Project-2, February 2005.

[8] Lei Lin, Yunping Zou, Jie Zhang, Xudong Zou, "Digital implementation of Diode-clamped Three Phase Three level SVPWM inverter," 2003.

[9] Bin Wu, PhD, "High power converters and AC drives," IEEE press, Wiley Inter Science.

[10] H. L. Liu, N. S. Choi and G. H. Cho, "DSP Based Space Vector PWM for Three-level Inverter with DC-link Voltage Balancing," EEE ICON,

[11] Subrata K. Momdal, Member, IEEE, Bimal K. Bose, Life Fellow, IEEE Vector PWM of Three level inverter extending operation into over modulation region," 2002.

[12] Armando Bellini-Stefano Bifaretti-Stefano Costantini, "A SVM technique for NPC Inverter," 2003.

[13] Bimal k. Bose, "Modern Power Electronics and AC Drives".

P. Satish Kumar (1), J. Amarnath (2) and S.V.L. Narasimham (2)

(1) Department of Electrical Engineering, University College of Engineering., Osmania University, Hyderabad, A.P.500 007, INDIA E-mail: satish_8020@yahoo.co.in

(2) J.N.T.University, Hyderabad, A.P, INDIA E-mail: amrnath_jinka@hotmail.com

P. Satish Kumar was born in Karimnagar, Andhra Pradesh, INDIA in 1974. He obtained the B.Tech degree in electrical engineering from JNTU College of Engineering, Kakinada, A.P., INDIA in 1996 and the M.Tech degree in power electronics from JNTU College of engineering, Hyderabad in 2003. He worked in various Private Engineering Colleges in Andhra Pradesh for more than eleven years as Associate Professor in the Department of Electrical and Electronics Engineering. Presently he is Assistant Professor in the Department of Electrical Engineering, University College of Engineering (Autonomous), Osmania University, Hyderabad, INDIA He is presently pursuing Doctoral degree from J.N.T.U, Hyderabad. His research interests include Power Electronics, Drives and Multilevel inverters.

J.Amarnath graduated from Osmania University in the year 1982, M.E from Andhra University in the year 1984 and PhD from J.N.T. University, Hyderabad in the year 2001. He is presently Professor in the Department of Electrical and Electronics Engineering, JNTU College of Engineering, Hyderabad, India. He presented more than 60 research papers in various national and international conferences and journals. His research areas include Gas Insulated Substations, High Voltage Engineering, Power Systems and Electrical Drives.

SVL Narasimham was born in Bellari, Karnataka State in India in 1961. He received his Bachelors Degree in Electrical and Electronics Engineering in 1982 from JNTU College of Engineering, Jawaharlal Nehru Technological University (JNTU). He obtained his Masters Degree in Electrical Power Systems in 1987, Masters Degree in Computer Science in 1995 and PhD in 2000 all from JNT University. He joined JNTU as Lecturer in Electrical Engineering in 1991 and is presently professor in Computer Science in School of Information Technology, JNTU. He is guiding many Ph.D. Students and presented more than 50 research papers in various conferences and Journals. He worked as Officer of Special Duty for Andhra Pradesh Transmission Corporation during May 2003 to February 2005. He worked as Senior Manager, e-projects on Deputation in Centre for Good Governance, a DFID funded AP State Government initiative, during April 2003 to March 2006, where he has exposure to various Government Systems including Power Sector, IT Initiatives and Irrigation. Dr. SVL Narasimham is a Fellow of Institution of Engineers India. His areas of interest are Energy Optimization and Audit, Distribution Systems in Electrical Engineering, Image Processing, Character Recognition, Home Automation and Software Engineering in Computer Science Areas.
Table I : Switching States of a Three Level Inverter.

Switching                  Switching conditions
Symbols
            [S.sub.11]   [S.sub.12]   [S.sub.13]   [S.sub.14]

    P           ON           ON          OFF          OFF
    O          OFF           ON           ON          OFF
    N          OFF          OFF           ON           ON

Switching      Output
Symbols        voltage
             ([V.sub.ao])

    P       +[V.sub.dc]/2
    O            0
    N       -[V.sub.dc]/2

Table II: Voltage Vector Duration.

Region             [T.sub.a]

  1       2k[T.sub.s] sin(60-[theta])
  2      2[T.sub.s][1-ksin([theta]+60)]
  3        [T.sub.s][1-2ksin[theta]]
  4        [T.sub.s][2ksin[theta]-1]

Region             [T.sub.b]

  1      [T.sub.s][1-2ksin([theta]+60)]
  2         2k[T.sub.s] sin[theta]
  3      [T.sub.s][2ksin([theta]+60)-1]
  4       2k[T.sub.s] sin(60-[theta])

Region             [T.sub.c]

  1       2k[T.sub.s] sin(60-[theta])
  2      [T.sub.s][2ksin(60-[theta])-1]
  3      [T.sub.s][2ksin([theta]-60)+1]
  4      2[T.sub.s][1-ksin([theta]+60)]

Table III: Switching Pattern in Each Region.

SECTION   SAMPLES   STATES        SWITCHING STATES

1.2       1         5-17-16-4     POO-PON-PNN-ONN
          2         4-16-17-5     0NN-PNN-PON-POO
          3         5-17-16-4     POO-PON-PNN-ONN
1.3       4         4-7-17-5      0NN-OON-PON-POO
1.4       5         6-18-17-7     PPO-PPN-PON-OON
          6         7-17-18-6     OON-PON-PPN-PPO
          7         6-18-17-7     PPO-PPN-PON-OON
          8         7-17-18-6     OON-PON-PPN-PPO
2.2       9         6-18-19-7     PPO-PPN-OPN-OON
          10        7-19-18-6     OON-OPN-PPN-PPO
          11        6-18-19-7     PPO-PPN-OPN-OON
2.3       12        9-19-7-8      OPO-OPN-OON-NON
2.4       13        9-19-20-8     OPO-OPN-NPN-NON
          14        8-20-19-9     NON-NPN-OPN-OPO
          15        9-19-20-8     OPO-OPN-NPN-NON
          16        8-20-19-9     NON-NPN-OPN-OPO
3.2       17        9-21-20-8     OPO-NPO-NPN-NON
          18        8-20-21-9     NON-NPN-NPO-OPO
          19        9-21-20-8     OPO-NPO-NPN-NON
3.3       20        11-8-21-10    NOO-NON-NPO-OPP
3.4       21        5-17-16-4     OPP-NPP-NPO-NOO
          22        4-16-17-5     NOO-NPO-NPP-OPP
          23        5-17-16-4     OPP-NPP-NPO-NOO
          24        4-16-17-5     NOO-NPO-NPP-OPP
4.2       25        10-22-23-11   OPP-NPP-NOP-NOO
          26        11-23-22-10   NOO-NOP-NNP-OPP
          27        10-22-23-11   OPP-NPP-NOP-NOO
4.3       28        12-23-11-13   OPP-NOP-NOO-NNO
4.4       29        12-23-24-13   OPP-NOP-NNP-NNO
          30        13-24-23-12   NNO-NNP-NOP-OPP
          31        12-23-24-13   OPP-NOP-NNP-NNO
          32        13-24-23-12   NNO-NNP-NOP-OPP
5.2       33        12-25-24-13   OOP-ONP-NNP-NNO
          34        13-24-25-12   NNO-NNP-ONP-OOP
          35        12-25-24-13   OOP-ONP-NNP-NNO
5.3       36        12-25-15-13   OOP-ONP-ONO-NNO
5.4       37        14-26-25-15   POP-PNP-ONP-ONO
          38        15-25-26-14   ONO-ONP-PNP-POP
          39        14-26-25-15   POP-PNP-ONP-ONO
          40        15-25-26-14   ONO-ONP-PNP-POP
6.2       41        14-26-27-15   POP-PNP-PNO-ONO
          42        15-27-26-14   ONO-PNO-PNP-POP
          43        14-26-27-15   POP-PNP-PNO-ONO
6.3       44        5-27-15-4     POO-PNO-ONO-ONN
6.4       45        5-27-16-4     POO-PNO-NPO-NOO
          46        4-16-27-5     NOO-NPO-PNO-POO
          47        5-27-16-4     POO-PNO-NPO-NOO
          48        4-16-27-5     NOO-NPO-PNO-POO

Table IV

Order                       2 level inverter   3 level inverter

    Input DC voltage              300V               300V
          Speed                 1442rpm            1443rpm
          T.H.D                  60.80%             31.14%
  Fundamental harmonic          109.3rms           109.3rms
Peak value of fundamental        154.5              155.5
   Switching frequency           2400Hz             2400Hz

Table V

Order of    2-level Harmonics at     3-level Harmonics at
Frequency   multiples of switching   multiples of switching
                  Frequency                Frequency

  1250               1.82                     2.45
  2450              26.91                    17.71
  3650               1.3                      0.71
  4850              20.54                     6.97
  7250              16.17                     3.88
  9650              11.33                     0.57

Table VI

Modulation           2-level VSI
  index      Fundamental    Vrms    T.H.D
             peak voltage

   0.7          136.3       96.36   73.47
   0.75         145.9       103.2   67.09
   0.8           154         109    60.19
   0.86          167        118.1   51.52

Modulation           3-level VSI
  index      Fundamental    Vrms    T.H.D
             peak voltage

   0.7           152        107.5   33.88
   0.75         153.7       108.1   31.34
   0.8          155.2       109.2   29.48
   0.86         157.7       111.5   29.51
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Title Annotation:pulse width modulation
Author:Kumar, P. Satish; Amarnath, J.; Narasimham, S.V.L.
Publication:International Journal of Applied Engineering Research
Article Type:Report
Geographic Code:1USA
Date:May 1, 2009
Words:2449
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