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A new design for a BiCMOS controlled current conveyor.


There are two basic technologies, known as bipolar and CMOS technology, for integrated circuit implementations. Bipolar technology maintains an advantage over CMOS in noise performance and higher transconductance. Also, it has better high frequency performance than its CMOS counterparts. On the other hand, CMOS transistors have low power consumption, high input resistance, and require a small silicon area compared with bipolar transistors. By combining these circuit technologies, the main advantages of each technology can be used. This technology is called BiCMOS and is useful in high frequency and low power analogue applications [1].

Second generation current conveyors (CCIIs) were introduced in 1970 [2]. Since their introduction, they have been used in numerous applications in the field of analogue electronics such as in filters, amplifiers, inductance simulators and, in particular, signal processing circuits. In 1995, the current controlled conveyor (CCCII) was introduced in bipolar technology [3] and later in BiCMOS [4] by Fabre. Parasitic resistance is essentially a disadvantage in electronic circuits. However, this intrinsic resistance, seen at port X, is used to advantage in current controlled conveyor circuits, because it can be easily controlled by biasing current. This advantage allows the design of numerous tunable functions [3], [5].

Second generation current conveyors designed using only CMOS technology has been proposed in the literature [6][8]. However, they are only able to operate at low frequencies. Therefore, the capability of applications is limited and these circuits exhibit severe frequency limitations.

A CCCII based on the mixed translinear loop using bipolar technology has also been described in the literature [3]. The CCCII is composed of NPN and PNP transistors. The use of PNP transistors in BiCMOS circuits offers reduced performance compared with NPN transistors. When PNP transistors are not used in CCCII, the frequency performance of the controlled current conveyor is better. This is because NPN transistors have higher electron mobility than PNP transistors. In the literature, current conveyors are designed by using PNP transistors for handling ac signals [9], [10]. However, the operating frequency of these circuits is highly low. These studies suffer from narrow bandwidth and circuit complexity. In order to avoid these problems, BiCMOS current conveyors using only two NPN transistors are proposed in this paper. In the designed circuits, the required bias current is achieved by employing only NMOS transistors and NPN transistors used for realizing the resistance RX. Also, the proposed circuit is eminently suitable for IC realization. In order to keep circuit complexity low and the design simple, fewer components are used in the circuit.

In this work BiCMOS controlled current conveyors, whose negative and positive parasitic resistance at port X can be controlled by biasing current, will be reviewed by this article. First, the theoretical analysis of the proposed circuits is presented. Then, the circuit analyses of the conveyors are presented. The performances of the proposed circuits are illustrated by Spice simulations. They show good agreement for all characteristics. To demonstrate the proposed circuit's easy applicability, it was used in a grounded inductance simulator and a bandpass filter.


In this section, the proposed controlled current conveyor with both positive resistance ([R.sup.+.sub.x]) and negative resistance ([R.sup.-.sub.x]) will be investigated.

A. CCCII with positive resistance

The proposed CCCII with ([R.sup.+.sub.x]) realization is shown in Fig. 1, where transistors [Q.sub.1] and [Q.sub.2] act as a transconductance amplifier to convert input voltage to output current.

[M.sub.1] and [M.sub.2] act as a simple current mirror where [I.sub.0] is the input bias current. The choice of MOS transistors to constitute the current mirrors is not arbitrary, since they allow a very weak consumption of power and dense integration, when [V.sub.y] and [V.sub.x] are applied from port Y and port X, respectively. According to the translinear principle, the difference between input voltages [V.sub.y] and [V.sub.x] of the transconductance amplifier is given by

[V.sub.y] - [V.sub.x] = [V.sub.BE1] - [V.sub.BE2] = [V.sub.T] (1n [I.sub.C1/[I.sub.S]] - 1n [I.sub.C2]/[I.sub.S])]] (1)

As shown in Fig. 1, [I.sub.C1] and [I.sub.C2] are the collector currents of the [Q.sub.1] and [Q.sub.2] transistors, respectively. In addition, [V.sub.T] is the thermal voltage, [V.sub.BE] is the junction voltage of the transistors and [I.sub.S] is the reverse saturation current of the transistors.

In this case, the collector currents of the transistors can be written by

[I.sub.0] [??] [I.sub.C1] + [I.sub.C2], (2)




The relationship of [I.sub.x] and input voltages of the transconductance amplifier is given by

[I.sub.x] = [I.sub.C2] - [I.sub.C1] = [I.sub.0] tanh ([V.sub.x] - [V.sub.y]/[2V.sub.T)]. (5)

If [V.sub.x] - [V.sub.y] << [2V.sub.T] is assumed from (5), then the function tanh[([V.sub.x] - [V.sub.y])/[2V.sub.T]] is approximately equal to([V.sub.x] - [V.sub.y])/[2V.sub.T.] The expression of this input current is

[1.sub.x] = [I.sub.0][V.sub.x] - [V.sub.y]/[2V.sub.T] (6)

When port Y of the CCCII is grounded and port X constitutes the input of the circuit (Fig. 1), the resistance [R.sub.x] of port X is the intrinsic resistance for the CCCII. [R.sub.x] is written as follows

[R.sub.x] = [2V.sub.T]/[I.sub.0] (7)

Derivations of the small-signal analysis can be expressed as

[i.sub.x] = [v.sub.x] x [g.sub.m2] - [v.sub.y] x ([g.sub.m4] x [g.sub.m1]/[g.sub.m5]) (8)

Since all transistors are operating at the same bias current, [g.sub.m5] = [g.sub.m4] and [g.sub.m1] = [g.sub.m2] = [g.sub.m] where

[i.sub.x] = [g.sub.m]([v.sub.x] - [v.sub.y]), (9)

thus, from (4) and (7) it can be seen that

[R.sub.x] = 1/[g.sub.m]. (10)

B. CCCII with negative resistance

The proposed CCCII with [R.sup.-.sub.x]realization is shown in Fig. 2.

As shown in Fig. 2, the CCCII with negative intrinsic resistance structure is the same as the other proposed CCCII with [R.sup.+.sub.x] structure in terms of components, but it uses different connections between the components in the circuit.

The same process formulated for CCCII with [R.sup.+.sub.x] is repeated for CCCII with [R.sup.-.sub.x]. An analysis of the circuit which operates as CCCII with [R.sup.-.sub.x], assuming all other transistors are matched, shows that the current [I.sub.x] is given by

[I.sub.x] = [I.sub.0][V.sub.y] - [V.sub.x]/[2V.sub.T] (11)

When port Y of the CCCII with [R.sup.-.sub.x] is grounded and port X constitutes the input of the circuit (Fig. 2), the intrinsic resistance [R.sub.x] is written as follows

[R.sub.x] = -[2V.sub.T]/[I.sub.0], (12)

As shown in (7) and (12), both positive and negative intrinsic resistance can be easily controlled by biasing current [I.sub.0].

CCCIIs with negative resistance realizations were introduced in [11], [12]. It is obvious that these circuits have complex circuit structures compared with the proposed circuit here.

C. Area mismatch of the CCCII

The effect of the differential pair mismatch of the CCCII in Fig. 1 can be defined as an inequality in the base-emitter areas of the transistors [Q.sub.1] and [Q.sub.2.] Such a mismatch between transistors can be given as:

{[I.sub.S1] = [I.sub.S] + [DELTA][I.sub.S]/2, {[I.sub.S2] = [I.sub.S] - [DELTA][I.sub.S]/2. (13)

A proportional mismatch in the collector transport saturation current [I.sub.S] is defined in (13). Thus, the biasing current [I.sub.0] obtained by using the MOS current mirror will be split between the [Q.sub.1] and [Q.sub.2] transistors in proportion to their [I.sub.S] values. If voltage [V.sub.y] and [V.sub.x] are grounded, the collector currents of the transistors will be found as follows:

{[I.sub.C1] = [I.sub.0]/2(1 + [DELTA][I.sub.S]/2[I.sub.S]), {[I.sub.C2] = [I.sub.0]/2(1 - [DELTA][I.sub.S]/2[I.sub.S]). (14)

The input current [I.sub.x] can be given by the following equation if the condition is [V.sub.x] - [V.sub.y] > 0

[I.sub.x] = [g.sub.m]([V.sub.x] - [V.sub.y)] - ([I.sub.0][DELTA][I.sub.S]/2[I.sub.S]), (15)

where [I.sub.S] is the collector transport saturation current of the [Q.sub.1] and [Q.sub.2] transistors. From the above equations, [R.sub.x] is written as follows

[R.sub.x] = ([V.sub.x] - [V.sub.y])/[I.sub.x] = 2[V.sub.T]/[I.sub.0] + [V.sub.T][DELTA][I.sub.S]/[I.sub.S][I.sub.x]. (16)


To validate the theoretical analysis, the circuits in Fig. 1 and Fig. 2 were simulated using models for the transistors of the type AMS S35 BiCMOS 0.35 [micro]m process. They were supplied under [+ or -]1.5 V.

The parasitic resistance of the proposed CCCII with [R.sup.+.sub.x] and CCCII with [R.sup.-.sub.x] for different biasing currents are shown in Fig. 3. The biasing current [I.sub.0] changes between 1 [micro]A and 50 [micro]A for both circuits.

This figure depicts the theoretical and simulation results. The theoretical calculation was performed using (7). As shown in Fig. 3, the simulation results approximately verified the theoretical consideration. The small difference between the curves is caused by a mismatch between transistors. Parasitic resistance can be approximately tuned from [+ or -]1.032 K[OMEGA] to [+ or -]51.6 K[OMEGA] for different biasing currents. In the literature, electronically tunable intrinsic resistance was used to advantage in CCCII [8], [12]. If the proposed circuit is compared with references [8], [12], it can be seen that this is better and preferable than these circuits. Although Zouaoui-Abouda's conveyor has ultra-high frequency response, the controllable range of the intrinsic resistance in the conveyor is limited between 0.58 K[OMEGA] and 2.8 K[OMEGA]. It is shown from Psychalinos's paper [12] that when the biasing current varies from 1 [micro]A to 50 [micro]A, the intrinsic resistance of the conveyor decreases approximately from 25.8 K[OMEGA] to 0.51 K[OMEGA]. Also, Psychalinos's circuits have more complex circuit structure containing many transistors than the proposed circuits in Fig. 1 and Fig. 2.

The simulated frequency response of the current gain from port X to port Z for the CCCII has been plotted in Fig. 4.

The -3dB bandwidth of the CCCII is located at 554.3 MHz for [I.sub.0] = 10 [micro]A.

Fig. 5 depicts the changing simulated percent total harmonic distortion (THD) plot versus peak to peak input current for the CCCII. THD % as a function of peak to peak magnitude of the input current is calculated for [I.sub.0] = 10 [micro]A and frequency = 1 MHz.

Fig. 5 shows that the THD % in the voltage at port X, when the peak to peak magnitude of the input current was changed from 1 [micro]A to 10 [micro]A, is found to vary from 0.026 % to 2.35 %. It is clear that the THD is within reasonable values. The input signal amplitude for achieving THD equal to 1% is 6.8 [micro]A. The signal quality remains excellent, as shown by the low values of the THD (simulated with a signal frequency of 1 MHz).

The power dissipation of the proposed circuit is found as 75.1 [micro]W for the biasing current 10 [micro]A. It has a good overall performance. BiCMOS is seen to have a clear advantage in power dissipation over bipolar technology.


A. Electronically tunable grounded inductance simulator

As an application, the proposed BiCMOS CCCIIs are used to build an electronically tunable grounded inductance simulator as shown in Fig. 6.

The circuit consists of a CCCII with [R.sup.+.sub.x], CCCII with [R.sup.-.sub.x] and a grounded capacitor. Based on the property of the proposed CCCIIs corresponding to (7) and (12), analysis of Fig. 6 shows that currents belonging to circuit are equal to

[I.sub.1] =- []/[R.sub.x1], (17)

[I.sub.2] = []/[sCR.sub.x1]([-R.sub.x2)], (18)

where [R.sub.x1] and [R.sub.x2] are the intrinsic resistances of the CCCII with [R.sup.+.sub.x], and CCCII with [R.sup.-.sub.x], respectively. As shown in Fig. 6, the input current of the simulator is relative to current [I.sub.2] as follows

[] = -[I.sub.2]. (19)

From (18) and (19), the input impedance of the simulator can be written as

[] = []/[] = [sCR.sub.x1][R.sub.x2]. (20)

As shown in (20), the equivalent inductance of the application circuit can be obtained as follows

[L.sub.eq] = [CR.sub.x1][Rx.sub.2]. (21)

The impedance values of the simulator relative to frequency for different [I.sub.0] are shown in Fig. 7, where C=50pF.

Fig. 7 depicts that the impedance of the circuit can be easily controlled by the biasing current of the conveyors and the inductance simulator contains only a grounded capacitor. Simulation results verify the theoretical background.

B. Bandpass filter

In order to present the applicability of the proposed circuits, a bandpass filter is used as an application. The tunable second order bandpass filter circuit shown in Fig. 8

When the two conveyors are dc biased by identical biasing current, the intrinsic resistances of the two conveyors are in consequence equal to [R.sub.x]. The transfer function of the bandpass filter with a gain equal to unity is characterized by:

[v.sub.0](t)/[](t) = [sC.sub.1][R.sub.x]/1 + [sC.sub.1][R.sub.x] + [s.sup.2][C.sub.1][C.sub.2][R.sup.2.sub.x], (22)

[[omega].sub.0] = 1/[R.sub.x][square root of [C.sub.1][C.sub.2]] (23)

Fig. 9 shows the simulated transfer response obtained for the filter with the different values of the biasing currents. These values are 20 [micro]A, 30 [micro]A and 40 [micro]A.

The values for the passive components in Fig. 8 are: [C.sub.1=4] pF and [C.sub.2=100] pF. The bandpass filter can be easily controlled by biasing current [I.sub.0]. Note that these simulated results are well correlated with the theoretical ones, especially for these high operating frequencies. The main advantages of the conveyor based bandpass filter are electronically tunability in a wide range and low power dissipation.


In this paper, new second generation BiCMOS CCCIIs were designed and their application to a grounded inductance simulator and a bandpass filter were tested. The proposed circuits were implemented in standard 0.35 [micro]m BiCMOS technology with no passive component, which is attractive for IC implementations. One of the reasons we used the BiCMOS technology is that it has the advantages of both bipolar and CMOS technologies.

Both CCCII with [R.sup.+.sub.x] and CCCII with [R.sup.-.sub.x] are the same in terms of having components, but different connections are used between the components in the circuit. Therefore the intrinsic resistance of the conveyor can be obtained as either positive or negative by using different connection structures. The proposed circuits were simulated using a Spice simulation program. The circuits' theoretical analysis was carried out, and the performance of the block circuit was confirmed through the Spice simulation results. The intrinsic resistance value of the proposed CCCII can be varied from [+ or -] 1.032 K[OMEGA] to [+ or -] 51.6 K[OMEGA] for different biasing current, with excellent correspondence between the theoretical and simulation results. Also, the proposed circuits have high frequency performance and low power dissipation.

Finally, such adjustable behavior in the proposed circuit, which has no passive component, is a good feature in general electronic circuit designs and we believe the circuit is rather convenient for BiCMOS IC realizations.

Manuscript received February 9, 2012; accepted April 29, 2012.


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H. Ercan (1), M. Alci (2)

(1) Department of Avionics, Erciyes University, 38039, Kayseri, Turkey, phone: +90 352 437 4901

(2) Department of Electrical and Electronics Engineering, Erciyes University, 38039, Kayseri, Turkey, phone: +90 352 437 4901
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Author:Ercan, H.; Alci, M.
Publication:Elektronika ir Elektrotechnika
Article Type:Report
Geographic Code:7TURK
Date:Jan 1, 2013
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