Printer Friendly

A high-performance energy efficient carry select adder using 32nm CMOS technology.

INTRODUCTION

Addition is the most common and often used in arithmetic operation son microprocessor, digital signal processor especially in digital computers. Also, it's a basic building block for the synthesis all other arithmetic operations. Hence, regarding the efficient implementation of an arithmetic unit the binary adder structures become a very critical hardware unit. In the case of digital adders, the speed of the addition is restricted by the time required to propagate a carry through the adder. Thus, the sum for each bit position in an elementary adder is generated serially only after the previous bit position has been summed and a carry being propagated into the next position.

In order to lower the power consumption of digital circuits the most apt technique is to lower the supply voltage. It is because of the quadratic dependence of the switching energy on the voltage. Here the sub threshold current is the main leakage component in CMOS devices when it is in the OFF state. Because, the CMOS device has an exponential dependence on the supply voltage level due to the induced drain barrier lowering effect. Similarly, when the device is the ON state and the supply voltage is reduced. Based on that voltage reduction, the device may occupy in the certain regions like super threshold regions, near-threshold regions, or subthreshold regions. When it is operating in the super threshold region, it will provide a lower delay and higher switching speed. And likewise, high leakage power as compared to that in the near or sub threshold regions. Then the logic gate delay and the leakage power of the device exhibits an exponential dependence on the supply voltages and threshold voltages in the sub threshold region. These voltages might be critically subject to the process and environmental variations in the nanoscale technologies. Then these variations may increase the uncertainties in the aforesaid performance parameters of the device. Then for the circuits that operating in the sub threshold region, the small sub threshold current may cause a very huge delay. As we know that the carry-select adder mainly consists of two ripple carry adders and a multiplexer. Hence by adding two n-bit numbers through a carry-select adder is done with the two adders.

Also, it may be compared with that of the sub threshold region of the device. It shows that the lower delay is compared with that in the sub threshold region of the device. In addition, the significant lower switching and leakage powers are compared with that in the super threshold region of the device. Moreover, the near-threshold operation of the device, uses the supply voltage levels near the threshold voltage of transistors. Because which is considerably less from the process and environmental variations as they are compared with the sub threshold region. Then the functioning of the device depending on the supply voltage and it has been the motivation for designing the circuits with dynamic voltage and frequency scaling.

Cmos technology:

Nowadays, the CMOS technology or the Complementary MOS technology is one of the most leading MOSFET technologies in the area of research in VLSI design. The CMOS technology is one of the top semiconductor technology for the designing of microprocessors, logic memories and application specific integrated circuits (ASICs). Because the main advantage of the CMOS technology over the NMOS and BIPOLAR technology is that there is a much lower power dissipation of the device. Unlike the NMOS or BIPOLAR circuits, the CMOS circuit has virtually no static power dissipation. Hence the power of the device is mainly dissipated in case if the circuit really switches. This may lead to allow to integrate more CMOS gates on an IC than in the NMOS or bipolar technology, resulting in the much-improved performance of the device. In the case of CMOS technology, both the N-type and the P-type transistors are used to realize the logic functions of the device. Here the same signal has been used to be turns on a transistor of one type and also used to turn off a transistor of the other type. This may lead the design of logic devices using the simple switches, without the need for the pull-up resistor.

The CMOS logic gates that shown in the Fig. 1, contains a group of n-type MOSFETs are arranged in a pull-down network between the output and the lower voltage power supply rail (Vss or quite often ground). The CMOS logic gates consists of a set of p-type MOSFETs that form a pull-up network between the output and the higher-voltage rail (often named Vdd) but the NMOS logic gates have the load resistor. Accordingly, if the gates of both the p-type and the n-type transistors are connected to the same input, then the p-type MOSFET will be on and the n-type MOSFET is off, and vice-versa.

One of the vital feature of the CMOS circuit is the duality that occurs between the PMOS transistors and NMOS transistors. As the CMOS circuit permits a path that always to exist from the output to either the power source or ground. To attain this, set of all paths to the voltage source must be complement of the set of all paths to ground.

CSA Architecture:

We know that he carry-select adder consists of two ripple carry adders and a multiplexer. Here the addition of a two n-bit numbers through a carry-select adder is done with two adders. That is in order to complete the calculation twice, one time with the hypothesis as the carry being zero and the other with a hypothesis of carry being one. In such a way, the two results are calculated, to acquire the correct sum, as well as the correct carry out. Hence the correct sum and carry are carefully chosen with the multiplexer when the correct carry in is known. The basic building block of the 16-bit carry-select adder [1], is shown in the Fig. 2.

As the block size of the adder should have a delay when the variable inputs are given to the circuit. Hence when inputs A and B are given to the carry out, that is equal to that of the multiplexer chain which leading into it, so that the carry out is calculated with just in time. Thus, the delay that obtained from the uniform sizing, where the ideal number of the full-adder elements per block is equal to that of the square root of the number of bits that being added, since that will yield an equal number of MUX delays.

If the two 4-bit ripple carry adders are multiplexed together, then the resulting carry out and sum bits are selected by the carry that are given as input. Subsequently, one of the ripple carry adder assumes a carry-in of 0, and the other assumes with a carry-in of 1. Formerly, the selecting which adder had the correct assumption with the actual carry-in that yields the correct result. Hence by adding two n bit numbers with carry select adder is done with the two adders. So, in order to obtain the calculation twice by one time with the assumption of the carry as 0 and other time with assumption of the carry 1. Which means that the carry select adder consists of two ripple carry adder in which one is assumed with a carry as 0 and other block with a carry as 1. Later the two results are attained then the correct sum, as well as the correct carry output is then selected with the help of the multiplexer when the correct carry input is known.

Existing cska structure:

In the existing structure for improving the efficiency of carry skip adder, a comprehensive approach is used. Here the speed improvement is achieved by applying the concatenation and incrimination methods to the conventional carry skip adder. Thus, by combining the concatenation and incrimination method to the regular carry skip adder the power consumption of the adder may be low. Here the existing structure is based on the combination of concatenation and the incrimination methods with the CSKA structure. Hence it provides with the ability to use simpler carry skip logics [1]. Thus, the logic replaces 2:1 multiplexers by AOI/OAI compound gates as shown in Fig.3.

Here the logic gates of the adder consist of fewer transistors, which have lesser delay, area, and smaller power consumption compared with the those of the 2:1 multiplexer. Also, note that, in this carry skip adder structure, the carry that propagates through the carry skip logics, becomes complemented. Consequently, the output of the even stages of skip logic, the complement of the carry is generated. Thus, the structure has a considerable smaller propagation delay with a somewhat lower area compared with those of the conventional one. Here the power consumption of the carry skip adder is a little bit more than that of the conventional adders. So, the internal structure of the proposed Carry skip adder [1] shown in Fig.3 in more detail. As the critical path of the CSKA structure, contains three parts. Then the first stage of these parts is the chain of FAs, then the second stage is the skip logic, and the final stage is the incrimination block. Thus, the incrimination block uses the intermediate results of the ripple carry adder block and the carry output of the previous stage to calculate the final sum of the stage.

Similarly, note that, the delay can be reducing considerably, by computing the carry output of each stage, and the carry output of the incrimination block is not used here. Hence for calculating the delay of the skip logic, the average of the delays of AOI and OAI gates are used, which are typically close to one another is used.

Proposed csa structure:

The proposed structure uses a carry select adder (CSA) with 32nm static CMOS technology. We know that the carry select adder includes a chain of full adders and multiplexers. Here the full adder adds binary numbers and also calculate the values that carried in as well as out. Thus, one-bit full adder may add three one-bit numbers, it may be written as A, B, and carry in; A and B are the operands, and the carry that given as input is a bit carried in from the next less significant stage. Later the full-adder is typically a component in a cascade of adders, bit wide a binary number. In case of the ripple carry adder each of full adder inputs a carry in, which is the carry out of the full adder. Thus, each full adder inputs a carry in, which is the carry out of the full adder. However, each full adder requires three levels of logic.

The schematic diagram for the CSA using static CMOS is shown in the Fig.4. Here the supply voltage is 1.2v. Thus, A, B and carry in are the inputs, sum and carry out are the outputs. As when all the inputs to the full adders are low, then the outputs are also low values. Similarly, when the two inputs of the adders are, low and carry in is high, then the sum is high and the carry out is a low value. Likewise, when all the inputs given to the adders are high, then the outputs are also high. So, if the output sum is an EXOR between the input A and half adder sum output with B and Carry in inputs.

That is a full adder circuit can be implemented with the help of the two half adder circuits. Hence the first half adder will be used to add A and B to obtain partial sum. Formerly the second half adder logic can be used to carry in to the sum produced by the half adder to get the final sum output. At that point any of the half adder logic produces a carry, there will be an output carry. Accordingly, the carry out will become the OR function of the half adder carry outputs.

We know that the multiplexer circuits consist of two inputs, they are denoted as A and B. Here the output is denoted as q. Here the main idea behind the multiplexing is that to transmit the two or more analog messages or the digital signals concurrently over a single communication channel, thus by sharing what might be an expensive resource. For illustration, in the case of the telephone industry, a number of the phone calls can be carried on a single wire. Another example is the home stereo system remote control which allows one to choose among the CD player, a DVD player, or cable TV. Thus, the sound systems having the digital output which may carry several channels over a single fiber optic cable. As in electronics, a multiplexer, or MUX, is a device that performs the multiplexing operation by forwarding the selected input into a single channel.

As we see that the multiplexer is a device that selects one of the several analog or digital input signals and forwards the selected input in to a single line. Then the multiplexer with 2ninputs has n select lines, which are used to select which input line to send to the output. As when all the inputs to the mux are low, then the output is also low. Similarly, when any of the input to the mux is high, then output is also high. Likewise, when all the inputs to the mux are high, then output is also high. So, multiplexers are commonly used to increase the amount of data that can be send over the network within a certain amount of time and bandwidth. Hereafter in the MUX one selection line (S) is used to select one of 2'=2 input lines, D0 and Dl, whose data is to be sent to the output (q).

Results and analysis:

In the proposed system the simulation results is obtained using Tanner EDA tool. The simulated waveform for the carry select adder is shown in the Fig.5.Here the inputs are A, B and Carry in. Also, Sum and Carry out are the output. From the output waveform, it is clear that the when all the inputs given are a low value, the outputs are also a low value. Correspondingly, when all the inputs to the adder are high, the outputs are also high. Thus, in a full adder circuit, it can be operated with the help of two half adder circuits. Here the first half adder will be used to add A and B to obtain the partial sum. Then main idea of multiplexing is to transmitting two or more analog messages or digital signals concurrently over a single communication channel, thus by sharing what might be an expensive resource.

Here the supply voltage is 1.2v. Here A, B and carry in are the inputs, sum and carry out are the outputs. As, when all the inputs to the full adders are low, then the outputs are also low values. When the two inputs of the adders are, low and carry in is high, then the sum is high and the carry out is a low value. When all the inputs given to the adders are high, then the outputs are also high. If the output sum is an EXOR between the input A and half adder sum output with B and Carry in inputs.

The power/energy consumption of the carry select adder is obtained using Tanner EDA tool.

Conclusion:

As the power, constituent factors in VLSI design limits the performance of any circuit. This paper presents a simple approach to reduce the power consumption of CSA architecture. The conventional carry select adder has the disadvantage of more power consumption. Here the concatenation method is used to design the CSA to improve the efficiency of the adder. The proposed CSA are designed and are implemented in Tanner EDA tool and the results are simulated in 32nm CMOS technology at supply voltage of 1.2 V. The power consumption of the carry select adder is 6.8[micro]W.
* BEGIN NON-GRAPHICAL DATA

Power Results
vdd gnd from time 0 to 1e-007
Average power consumed -> 6.882760e-005 watts
Max power 6.882760e-005 at time 1e-007
Min power 6.882760e-005 at time 0

* END NON-GRAPHICAL DATA

* Parsing                 0.01 seconds
* Setup                   0.11 seconds
* DC operating point      0.12 seconds
* Transient Analysis      0.06 seconds
* Overhead                2.13 seconds
* Total                   2.43 seconds

* Simulation competed with 6 Warnings

* End of T-Spice output file


REFERENCES

[1.] Neethumol, A., S. Gnanamurugan, 2016. "Designing of High performance carry select adder using CMOS technology" IJCAT, 3(11).

[2.] Milad Bahodari, Mehadi Kamal, Ali-Afzali-Kusha, 2016. "High speed and Energy Efficient Carry Skip adder operating under a wide range of supply voltage levels" IEEE Trans. VLSI Syst., 24(2).

[3.] Jain., S., 2012. "A 280mV to 1.2V wide operating range IA-32 processor in 32nm CMOS", IEEE Int. Solid State Circuits Conf. Dig. Tech. Papers (ISSCC), 40(1): 44-51.

[4.] Su. Y.S., D.C. Wang, S.C. Chang and M. Marek Sadowska, 2011. "Performance optimization using variable latency design style," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 19(10): 1874-1883.

[5.] Markovic, D., C.C. Wang, L.P. Alarcon, T.T. Liu and J.B. Rabaey, 2010. " Ultra low power design in near threshold region", Proc. IEEE, 98(2): 237-252.

[6.] Chen, Y., 2010. "Variable-latency Adder (VL-Adder) designs for low power and NBTI Tolerance" IEEE Trans. (VLSI) Syst, 18(11): 1621-1624.

[7.] Ghosh, S., D. Mohaputra, G. Karakonstantis and K. Roy, 2010. "Voltage Scalable High-Speed Robust Hybrid Arithmetic Units Using Adaptive Clocking ",IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 18(9): 1301-1309.

[8.] Zlatanovici, R., S. Kao and B. Nikolic, 2009. "Energy-Delay Optimization of 64-Bit Carry-Look ahead Adders With a 240 ps 90 nm CMOS Design Example" IEEE J. Solid State Circuits, 44(2): 569-583.

[9.] He, Y. and C.H. Chang, 2008. "A Power-Delay Efficient Hybrid Carry-Look ahead / Carry-Select Based Redundant Binary to Two's Complement Converter" IEEE Trans. Circuits Syst. I Reg. Papers, 55(1): 336-346.

[10.] Okalobdzijia, V.G., B.R. Zeydel, H.Q. Dao, S. Mathew, R. Krishnamurthy, 2005. "Comparison of High-Performance VLSI Adders in the Energy-Delay Space ", IEEE Trans. VLSI Syst., 13(6): 754-758.

[11.] Mathew, S.K., M.A. Anders, B. Blochel, T. Nguygen, R.K. Krishnamurthy and S. Borkar, 2005. " A 4GHz 300-mW 64-bit integer execution ALU with dual supply voltages in 90nm CMOS," IEEE J. Solid State Circuits, 40(1): 44-51.

(1) A. Neethumol, (2) S. Gnanamurugan

(1) PG Student, Department of ECE Vivekanadha College of Engineering for Women, Namakkal India

(2) Assistant Professor, Department of ECE, Vivekanandha College of engineering for women, Namakkal,I ndia

Received 28 January 2017; Accepted 22 March 2017; Available online 28 April 2017

Address For Correspondence:

A. Neethumol, PG Student, Department of ECE Vivekanadha College of Engineering for Women, Namakkal, India

E-mail: 05neethuajayan@gmail.com

Caption: Fig. 1: CMOS logic gate.

Caption: Fig. 2: Block diagram of 16-bit Carry Select Adder.

Caption: Fig. 3: Block diagram of CSKA.

Caption: Fig. 4: Schematic diagram for the CSA.

Caption: Fig. 5: Simulated waveform of CSA.
COPYRIGHT 2017 American-Eurasian Network for Scientific Information
No portion of this article can be reproduced without the express written permission from the copyright holder.
Copyright 2017 Gale, Cengage Learning. All rights reserved.

Article Details
Printer friendly Cite/link Email Feedback
Author:Neethumol, A.; Gnanamurugan, S.
Publication:Advances in Natural and Applied Sciences
Date:Apr 30, 2017
Words:3192
Previous Article:Design and Implementation of multiplier using CMOS adiabatic logic.
Next Article:ECG front end data acquisition system with CMOS technology.
Topics:

Terms of use | Privacy policy | Copyright © 2019 Farlex, Inc. | Feedback | For webmasters