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A designer's survival guide to high-speed serial links: pre-emphasis and backdrilling can help you avoid being a casualty in the battle for signal integrity.

At the dawn of the personal computer era in the early 1980's, clock frequencies were about 20 MHz and no one cared about signal integrity. Interconnects were transparent. The physical design of systems was about getting the connectivity right, about fitting all the components on the board and about managing the temperature verses fan noise.

Then came the high-performance era of the 1990s, when clock frequencies increased to 200 MHz and above. Signal integrity became the new mantra. If you did not design the product for signal integrity, the product might not work. The physical design had to take into account controlled impedance interconnects and a linear topology, a termination strategy, minimized return path inductance for low ground bounce, and a low impedance power distribution network.

Now we are in the 21st century, when high-speed serial links with data rates in excess of 2 GHz proliferate. To design products that work the first time now requires doing all the above, plus designing for controlled differential impedance, minimizing discontinuities, controlling the losses in the interconnects, optimizing the vias, using silicon technology to add pre-emphasis and equalization, and don't forget, balancing the design and technology selection for lowest possible cost.

The one lesson we have learned over the last 20 years is that as speed goes up, our luck and hope goes down. To survive in this new era, we can't rely on luck anymore; we must rely on being smarter in how we design (1).

Controlled Differential Impedance

Differential impedance is the instantaneous impedance the difference signal sees as it propagates down a differential pair of transmission lines (2). Just as with a single-ended signal, the impedance the difference signal sees must be constant along its path, or the signal will suffer reflections and the received signal will be distorted. The differential impedance of all the traces in the board must be at the target value, typically 100 [ohm], in order to assure acceptable received signal amplitude and rise time.

This is primarily achieved by the selection of line widths, spacing, dielectric thickness and knowing the dielectric constant of the laminate materials. The only way of accurately balancing the board stackup and evaluating the tolerance buildup is with a 2D field solver. FIGURE 1 explores how the spacing between two stripline traces affects their differential impedance. An easy-to-use, accurate 2D field solver is an essential tool to survive in this new regime.


It is not the losses in the interconnects that cause problems in high-speed serial links--it is the frequency dependency of the losses. Both conductor loss and dielectric loss absorb more of the higher-frequency components than of the low-frequency components. This means that if you launch an ideal square wave into an interconnect, the rise time will degrade and get longer as it propagates, because the higher frequencies that make up the sharp edge are removed. This is illustrated in FIGURE 2.


This rise time degradation causes most of the significant problems with high-speed serial interconnects, such as intersymbol interference (ISI), deterministic jitter and collapse of the eye diagram. It can be most easily described as the attenuation or loss in the signal as a function of frequency.

Conductor loss is frequency-dependent due to skin depth effects. The cross-sectional area for current to travel through a conductor decreases into a thinner and thinner perimeter shell as frequency goes up. This increases the series resistance of both the signal and return conductors at higher frequency.

The only way to reduce the losses from the conductors' series resistance is by using wider lines. But to use wider lines while still maintaining the target impedance also requires either thicker dielectric layers or lower dielectric constant.

Of course, there is a limit to the total thickness of a board. With as many as 40 layers, in .250" total thickness, the maximum dielectric thickness is on the order of .006" already. And thicker boards will be more expensive due to material and drilling costs. Further, as we shall see, a thicker board also means longer via stubs, which will cause additional signal integrity problems.

Balancing the widest line for lowest rise time degradation, thinnest total board and acceptable cost can only he done with a simulation tool that includes lossy line effects, such as Mentor Graphics HyperLynx or Agilent Technologies ADS.

The second source of frequency-dependent loss comes from the dissipation factor of the laminate. This material property is a measure of the dipoles in the laminate, which can rotate in the applied field of the signal and suck out energy from the signal. The higher signal frequency components will rotate the dipoles faster and cause more heat generation. Even though the dissipation factor of most materials is constant with frequency, the attenuation from the dissipation factor will increase with higher frequency. A low dissipation factor will minimize the rise time degradation.

Insertion loss is a common metric to quantify the frequency-dependent loss of a signal as it propagates down an interconnect. This can be further refined as the attenuation in dB per inch of interconnect. A larger and more negative dissipation factor will mean less high-frequency signal and longer rise time, a bad thing. FIGURE 3 shows an example of the insertion loss for both conductor loss and dielectric loss.


As a rough rule of thumb, with many popular SERDES chips the typical acceptable attenuation might be as high as -10 dB at the bandwidth of the high-speed serial link, which is about half the bit rate. For a XAUI interface, at 3.125 Gbps the bandwidth is about 1.6 GHz. If the interconnect length were 40 inches, the acceptable attenuation per length would be about -10 dB/40 inches, or ~ -0.25 dB/inch, at 1.6 GHz.

In the example above, the total attenuation from the conductor loss and dielectric loss would be -0.12 dB/inch + -0.15 dB/inch = -0.27 dB/inch. This is above the estimated acceptable limit, which suggests a marginal design.

For a robust design, either the line width must be increased, the dissipation factor decreased, the interconnect length decreased, the SERDES noise margin increased, or silicon processing (i.e., pre-emphasis in the drivers) would have to be used.

The Power of Pre-emphasis

The problem with attenuation in interconnects isn't the attenuation--it's the frequency dependence that causes rise time degradation. If we know how much the higher frequencies will be attenuated and put an extra amount of these into the signal when it is launched, we might be able to see a sharper rise time at the receiver. The technique of adding high-frequency components into the launched signal is called pre-emphasis.

An example of the time domain waveform of the launched signal with pre-emphasis is shown in FIGURE 4.


There is an extra pulse at the transitions. When this signal travels down the interconnect, the extra high-frequency components will be absorbed, flattening the waveform back into a more normal looking waveform. Pre-emphasis is a powerful technique of recovering a signal at the far end of a lossy line.

In FIGURE 5 is displayed the eye diagram of a XAUI signal, received after 57 inches in an FR-4 interconnect. There is so much frequency-dependent attenuation that all the bits are grossly distorted and cannot be read with any certainty. This interconnect is completely unusable.


However, with pre-emphasis, extra high-frequency components are added to the signal and the frequency-dependent attenuation sucks out these extra components, leaving behind a much more usable signal. This is shown in FIGURE 6.


The combination of conventional FR-4 boards and pre-emphasis in the drivers is a powerful combination for designing successful high-speed serial links. The higher the bandwidth, the greater the need for wider lines, lower dissipation factor and silicon processing.

Though pre-emphasis can overcome losses in the interconnect, it cannot overcome the sharp resonances from via stubs. Ultimately, these stubs will be a fundamental limit to the bit rate for backplane interconnects.

If conductor and dielectric loss were the only processes decreasing the insertion loss with frequency, pre-emphasis could compensate. Unfortunately, the stubs created by through vias can act as resonators and absorb a very large amount of the signal energy in narrow frequency bands. An example of the measured insertion loss of a backplane channel with and without a via stub is shown in FIGURE 7.


The resonator is created when a signal uses a through via to transition from two closely spaced layers, such as between layers 1 and 4 or 2 and 5 in a 20- to 30-layer board. The rest of the via stub is left hanging onto the signal trace. This stub has a resonant frequency based on when its length matches a quarter of a wavelength.

When the stub length is .200", this is about 7.5 GHz. In addition, any pads placed on unused layers to anchor the via, often called nonfunctional pads (NFP), will add capacitance to the stub and decrease the resonant frequency. Typical via stub resonant frequencies are in the 4-6 GHz range.

If this resonance is at a frequency equal to half the bit rate, there will be no eye open at the receiver. The insertion loss for the primary, highest bit rate signal could easily be -60 dB. This is less than 0.1% of the signal to the receiver.

Even lower frequency bit rates can suffer from via stub resonances, if their bandwidths are riding on the edge of the resonance curve. The most effective way of eliminating this problem is to move the via stub resonant frequency as high as possible, by using as short a via stub as possible. This can be done by removing NFPs from unused layers, limiting layer transitions to those near the outer layers, and backdrilling any stubs that might be left.

Backdrilling is the process of redrilling the bottom of the via with an oversized drill bit, after the through via has been plated. This removed the plated through hole that is not being used and eliminates the resonating stub. FIGURE 8 shows an example of an as-fabricated through-hole via in an 18-layer board, and a similar via that has been backdrilled to remove the long stub.


Backdrilling has become the de facto standard in all high-performance backplanes used in systems at 5 Gbps and above. To allow scalability of a backplane that may be first used at 2.5 Gbps or even 3.125 Gbps, so that it could be used later in life at 5 Gbps, backdrilling is often employed. This way, higher bit rate cards can be plugged into this legacy backplane and still operate acceptably.

Beginning of an Era

In this new era of high-speed serial links operating at 2 Gbps and above, a new set of signal integrity concerns must be considered for a system to work the first time. In addition to all the other signal integrity problems like terminations and topologies, crosstalk, ground bounce and power distribution, now we must design out differential impedance problems, deal with losses and include via stub effects.

To survive this new set of minefields requires new skills, new tools and new technologies. The elements of survival include the use of 2D field solvers to accurately design the stackup and routing for differential pairs, the selection of optimal dielectric materials with low dielectric constant to allow wide lines and thin boards, low dissipation factor for low insertion loss and the use of silicon processing such as pre-emphasis. Finally, techniques to minimize the length of via stubs such as backdrilling are essential.

Now interconnects are not only not transparent but are the dominant factor determining whether a large, high-performance system will work the first time, every time. By paying careful attention to all of these important issues, you can be successful in this era and earn the right to face the challenges of the next generation of high-performance systems.


(1.) This paper is based on Online Lecture 184, A Designer's Survival Guide to High-Speed Serial Links, posted on www.bethe To view this lecture for free, enter coupon code PCDM0507.

(2.) Bogatin, Eric, Signal Integrity--Simplified, Prentice Hall, 2003.

ERIC BOGATIN is the CTO at IDI, and president of Bogatin Enterprises. He can be reached at
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Author:Bogatin, Eric
Publication:Printed Circuit Design & Manufacture
Article Type:Cover Story
Date:Jun 1, 2005
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