A broadband low power high isolation double-balanced subharmonic mixer for 4G applications.
Due to the popularization of mobile internet in recent years, academia and industry focus on high speed data transmission. Long Term Evolution release 10 (LTE-Advanced) and Worldwide Interoperability for Microwave Access (WiMAX) are the candidates for nowadays 4G system. The operating bands for LTE-Advanced and WiMAX are 698-3600 MHz and 2305-5850 MHz, respectively. WiMAX technology based on orthogonal frequency division multiplexing access (OFDMA) is specified in the IEEE 802.16m standard. Both of the two techniques supports different modulations, such as QPSK, 16QAM, and 64QAM. In the physical layer design, the two techniques adopt orthogonal frequency division multiplexing access (OFDMA) and discrete Fourier transform spread orthogonal frequency-division multiplexing (DFTS OFDM).
In recent years, superheterodyne and direct conversion are two main architectures for modern receiver designs [1-6]. Compare with the superheterodyne receiver, the direct conversion receiver (DCR) is the most attracting architecture to realize a high level of integration, the elimination of the off-chip filter, and system-on-a-chip (SoC). Even though DCR has merits such as low cost, low power, and low complexity, it still suffers from several drawbacks: second-order distortion, flicker (1/f) noise, and DC offset. These drawbacks are the main design challenges of a DCR. In radio frequency (RF) receivers, mixers are important components which provide the frequency translation from RF signals to the intermediate frequency (IF) signals called "down-convert". DC offset of a mixer worsens the operation of the following stages. The main sources of DC offset are the leakages caused by the finite isolation between the local oscillator (LO) and RF ports of a mixer. A strong, nearby signal, including the receiver's own LO, can mix with itself down to zero IF (this is known as "LO self-mixing") and generate a DC level that appears as interference at the center of the desired band. Figure 1 illustrates the block diagram of the direct conversion receiver. There are three paths which denote different types of the LO self-mixing. The leakage of the LO signal reradiates from the antenna is shown in the path 1. The leaked LO signal may be reflected from buildings or moving objects and recaptured by the same antenna. Path 2 shows the recaptured phenomenon. The received power level can vary rapidly with fading and multipath reception and results in a time-varying or dynamic DC offset. Path 3 represents the LO leakage of the LO signal to the input of the low noise amplifier (LNA) and mixer. The LO leakage is difficultly mitigated by adopting filters [7-10]. The leakage signal mixes with the LO signal and results in a constant DC offset [11,12]. As a result, the DC offset will affect the DC operation point of the following stage circuits.
Up to now, lots of methods have been proposed to suppress DC offsets of the mixer due to the finite port-to-port isolation. A mixer adopting a frequency doubling stage at the output of the LO port to mitigate the LO self-mixing is also called "subharmonic mixer" [13-16]. The subharmonic mixer is a compact architecture without additional DC offset calibration circuits. However, the revealed single-balanced architectures are still suffered from the lower isolation and narrowband operation issues. The poor isolation characteristic of the single-balanced subharmonic mixer leads to DC offsets due to the large LO leakage and the 2 x LO frequency leakage. In this paper, a 2.3-5.8 GHz broadband mixer using a single-to-differential frequency-doubling technique is proposed. Section 2 of this paper describes the background between a single-balanced subharmonic mixer and the proposed mixer. Section 3 presents the measurement results of the mixer. Finally, conclusions in Section 4 are summarized.
2. DESIGN METHODOLOGY OF MIXERS
2.1. Single-balanced Subharmonic Mixer
Figure 2 illustrates the conventional single-balanced subharmonic mixer . [M.sub.1] and [M.sub.2] denote the LO frequency-doubling stage. [M.sub.3] and [M.sub.4] represent the class-A transconductor stage. [M.sub.1]-[M.sub.4] operate in the saturation region and the saturation current is given by
[I.sub.dsn] = K[([V.sub.gsn] - [V.sub.th]).sup.2]/1 + [theta]([V.sub.gsn] - [V.sub.th]) (1)
where K is a constant depending on the technology and the transistor dimensions, n is an integer. Parameter [theta] approximately models source series resistance, mobility degradation because of the vertical field, and short-channel effects such as velocity saturation . To derive the frequency-doubling effect, (1) is simplified as
[I.sub.dsn][approximately equal to] K[[[V.sub.gstn] + [A.sub.LO] cos([[omega].sub.LO]t)].sup.2] (2)
where [V.sub.gstn] denotes the overdrive voltage, and [A.sub.LO] cos([[omega].sub.LO]t) represents the input LO signal. From (2), the drain currents of [M.sub.1] and [M.sub.2] are calculated by
[I.sub.ds1] = K[[[V.sub.gst1] + [A.sub.LO] cos([[omega].sub.LO]t)].sup.2] (3)
[I.sub.ds2] = K[[[V.sub.gst2] + [A.sub.LO] cos([[omega].sub.LO]t)].sup.2] (4)
The overall current [I.sub.d] is given by
[I.sub.d] = [I.sub.ds1] + [I.sub.ds2] (5)
[MATHEMATICAL EXPRESSION NOT REPRODUCIBLE IN ASCII] (6)
where 2[I.sub.D] is the total DC current of [M.sub.1] and [M.sub.2], [i.sub.lo] the LO small signal current, and [I.sub.LO] the LO offset current. From (6), the 2 x LO frequency signal is obtained. The IF frequency is demonstrated as
[[omega].sub.IF] = [[omega].sub.RF] - 2[[omega].sub.LO] (7)
where [[omega].sub.IF], [[omega].sub.RF], and [[omega].sub.LO] represent IF, RF, and LO frequency, respectively. According to (7), the subharmonic architecture can suppress the LO leakage due to half of input LO frequency. It also alleviates the specification of voltage-controlled oscillator (VCO) in the RF receiver design. However, owing to poor isolations between RF, LO and IF ports, the single-balanced architecture still suffers from LO leakage and the 2 x LO frequency leakage.
2.2. Double-balanced Subharmonic Mixer
The proposed broadband high isolation double-balanced subharmonic mixer adopting the single-to-differential frequency-doubling technique is depicted in Figure 3. The single-to-differential frequency-doubling stage consists of [M.sub.1]-[M.sub.5]. [M.sub.1] and [M.sub.2] are operated in the saturation region. The diode-connected [M.sub.1] and common-source amplifier [M.sub.2] provide the single-to-differential mechanism and apply two mutually out-of-phase current signals. [M.sub.3] and [M.sub.4] realize the LO frequency-doubling stage. It is often driven by the power from LO in the RF front-end. It will be complex when a mixer requires large LO power because it is difficult to design a local oscillator with high output power in a portable system. The DC operation point of the LO frequency-doubling stage will decide the switch driven power. To make [M.sub.3]-[M.sub.4] acts normally with moderate driven power. The transistors are biased in the saturation region. [M.sub.5] is adopted to compensate the loading effect of [M.sub.3] and [M.sub.4]. The control voltage [VB.sub.CON] of [M.sub.5] is used for adjusting the mismatch between two signal paths.
The RF transconductor stage which consist of [M.sub.6]-[M.sub.9] is realized by the anti-parallel configuration with respect to IF stage. [M.sub.6]-[M.sub.9], [M.sub.3], and [M.sub.4] are biased by the bias tee architecture in the impedance matching network. The matching networks of RF/LO ports consisted of [R.sub.1]-[R.sub.4], [C.sub.1]-[C.sub.4], and [L.sub.1]-[L.sub.4] provide the impedance matching from 2.3 GHz to 5.8 GHz. [VB.sub.RF] and [VB.sub.LO] are the DC bias voltages of RF and LO ports. This transconductor stage converts the input RF signal into the small signal current. The small signal current is multiplied by the 2 x LO frequency signal and down converted to IF. It is translated into the voltage signal by the load stage consisted of [M.sub.10], [M.sub.11], [R.sub.5] and [R.sub.6]. The load stage can provide output impedance via the resistive load of [R.sub.5] and [R.sub.6], and appropriate voltage swing headroom by the transistors [M.sub.10] and [M.sub.11]. The output impedance of the source follower stages, [M.sub.12], [M.sub.13], [R.sub.7], and [R.sub.8], are specified to 50 [ohm] for measurement purpose. However, the conversion gain will be reduced by the source follower stages.
3. MEASUREMENT RESULTS
The mixer was fabricated in tsmc 0.18 [micro]m Mixed Signal CMOS RF technology. The operating band is from 2.3 GHz to 5.8 GHz. Because IF is fixed at 20 MHz and the proposed double-balanced subharmonic architecture, from (7), LO frequency is equal to
[[omega].sub.LO] = ([[omega].sub.RF] - [[omega].sub.IF])/2, (8)
The input LO frequency is from 1.14 GHz to 2.89 GHz. Measurements of the differential RF/LO/IF signals were provided by coplanar Ground-Signal-Ground-Signal-Ground (GSGSG) 100 [micro]m pitch on-wafer probes measurement system based on the Agilent E4407B spectrum analyzer. The differential RF/LO signals were generated using the Anaren 180[degrees] Balun. The single-ended IF signal was produced by the 180[degrees] Mini-Circuits ZMSCJ-2-1 Balun. The supply and bias voltages are connected by three separate pads for probing through a conventional 7-pin DC probe. The losses of the probes and cables were calibrated by the PNA 5230A network analyzer.
The active current of the mixer is about 1.64 mA from a 1.8 V supply voltage. Figure 4 illustrates the measured conversion gain versus LO power at 5.8 GHz. Measurement of different LO powers at 2.3GHz, 3.5GHz and 5.8GHz are shown in Figure 5. The LO power is 4 dBm to optimize the mixer performance. The simulated and measured conversion gains are illustrated in Figure 6 with RF varied from 2.3 GHz to 5.8 GHz. Owing to the process variation, there will be differences between the simulated and measured conversion gains. The maximum power conversion gain of the proposed mixer is 7.1 dB at 3 GHz. IIP2 and IIP3 of the mixer is calculated by using a two-tone testing. The frequency spacing in the two-tone test is set to be 250 kHz which is the channel spacing in a 4G system. The down-converted IF signals are at 19.875 MHz and 20.125 MHz, and the third-order intermodulation (IM3) distortions are at 19.625 MHz and 20.375 MHz, respectively. The extrapolation plot of IIP3 is illustrated in Figure 7 and the IIP3 is -9.9dBm at 3.8 GHz. Figure 8 represents the simulated and measured IIP3 versus input radio frequency. The second-order intermodulation (IM2) distortions is at 250 kHz. Figure 9 shows an extrapolation plot of IIP2 at 3.8GHz, the maximum IIP2 is 33.5 dBm. The measured IIP2 at various input frequency is shown in Figure 10. The proposed mixer demonstrates superior IIP2 from 2.3 GHz to 4.3 GHz. Due to the variation of the parasitic capacitance, Metal-Insulator-Metal (MIM) capacitance, and inductance, IM3 and IM2 are suppressed from 3.5 GHz to 4 GHz. Therefore, IIP3 and IIP2 will increase.
In the LO/RF, LO/IF, and RF/IF isolation measurements, the IF balun needs to be replaced with Anaren 180[degrees] Balun due to the operated frequency limitation and measurement accuracy. Figure 11 illustrates the LO-RF and LO-IF isolation characteristic versus LO frequency. Due to the device mismatch, the difference of routing length, and S22 variation of the LO port, the LO-RF isolation increases from 1.8 GHz to 2.3 GHz, respectively. The LO-to-RF isolation is better than 66.4dB, and the LO-to-IF isolation is higher than 58.7dB from 2.3 GHz to 5.8 GHz. Figure 12 shows the 2 x LO-RF and 2 x LO-IF isolation characteristic alongside the various 2 x LO frequencies. The minimum 2 x LO-to-RF and 2 x LO-to-IF isolation characteristic are 60.5 dB and 56.9dB, respectively. Figure 13 represents the RF-IF isolation characteristic versus LO frequency. The overall measured isolation of the proposed mixer demonstrates excellent performance over previous SHMs [19-23]. The chip micrograph of the mixer is depicted in Figure 14. It occupies a compact area of 1.33 x 1.24 [mm.sup.2]. All passive components are implemented on a chip. The symmetrical placement and routing can reduce the magnitude mismatch and phase mismatch of the differential signals.
Table 1 summarizes the experimental results of the proposed mixer. The proposed mixer reveals excellent properties of the port-to-port isolation and lower power consumption.
A 1.8 V CMOS broadband double-balanced subharmonic mixer for 4G applications is presented in this paper. The proposed mixer performs high isolation characteristics with the single-to-differential frequency-doubling technique. The mixer operates from 2.3 GHz to 5.8 GHz and converts to the IF signal frequency of 20 MHz by mixing with the LO frequency from 1.14 GHz to 2.89 GHz. The mixer achieves conversion gain of 7.1 dB, IIP2 of 33.5 dBm, IIP3 of -6.9 dBm, noise figure of 19.6dB. The superior port-to-port isolations were measured with RF-IF isolation of 62.3dB, LO-to-RF isolation of 82.8dB, LO-to-IF isolation of 66.5 dB, 2 x LO-to-RF isolation of 73.2 dB, and 2 x LO-to-IF isolation of 81.7dB. The total power consumption including the buffer circuitry is 2.95 mW. Because the behaviors of the mixer exhibit relatively high isolation and low power consumption, the proposed mixer is suitable for direct conversion receiver applications.
The chip fabrication measurement were supported by the National Chip Implementation Center (CIC) of Taiwan, R.O.C.
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Hung-Che Wei (1), Chih-Lung Hsiao (2), *, and Ro-Min Weng (3)
(1) Department of Electronic Communication Engineering, National Kaohsiung Marine University, No. 142, Haijhuan Rd., Nanzih Dist., Kaohsiung City 81157, Taiwan, R.O.C.
(2) Department of Electrical Engineering, Lunghwa University of Science and Technology, No. 300, Sec. 1, Wanshou Rd., Guishan Shiang, Taoyuan County 33306, Taiwan, R.O.C.
(3) Department of Electrical Engineering, National Dong Hwa University, No. 1, Sec. 2, Da Hsueh Rd., Shou-Feng, Hualien County 97401, Taiwan, R.O.C.
Received 25 January 2013, Accepted 13 March 2013, Scheduled 16 March 2013
* Corresponding author: Chih-Lung Hsiao (CL_Hsiao<Qmail.lhu.edu.tw).
Table 1. Performance summary of mixers. Ref.    This work Process ([micro]m) 0.18 0.18 0.18 0.18 Supply Voltage (V) 2.75 1.8 0.8 1.8 RF (GHz) 12.1 5.25 3~5 2.3~5.8 Conversion Gain (dB) 5.8 8.3 0.8~4.4 4.3~7.1 IIP2 (dBm) 17 31.2 N.A. 19.6~33.5 IIP3 (dBm) -2 0 N.A. -6.9~-10.5 30 N.A. 40~50 47.2~62.3 LO-IF Isolation (dB) 68 43 36~54 58.7~66.5 LO-RF Isolation (dB) 71 33 44~56 66.4~82.8 2 x LO-IF Isolation (dB) 55 19 N.A. 56.9~81.7 2 x LO-RF Isolation (dB) 52 58 N.A. 60.5~73.2 SSB Noise Figure (dB) 18 24.5 N.A. 19.6~22.9 Power Consumption 113 4.95 16 2.95 (mW) Chip Area ([mm.sup.2]) 0.85 x N.A. 1.78 x 1.33 x 0.85 1.39 1.24
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|Author:||Wei, Hung-Che; Hsiao, Chih-Lung; Weng, Ro-Min|
|Publication:||Progress In Electromagnetics Research|
|Date:||Jun 1, 2013|
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