A Miniaturized 4:1 Unequal Wilkinson Power Divider Using Artificial Transmission Lines and Double-Sided Parallel-Strip Lines.
Power dividers are widely used as one of the key components in various microwave applications for power allocation and synthesis. Wilkinson power divider is widely used due to its high return loss and isolation as well as low insertion loss by structure of simplicity. However, a conventional Wilkinson power divider has weakness in size, because it is composed of quarter wavelength transmission lines. In addition, for a 4: 1 unequal Wilkinson power divider, high impedance line of 158.1 Q is difficult to be achieved by conventional microstrip transmission line.
Recently, one type of artificial transmission line (ATL) has been proposed which can equivalently achieve arbitrary characteristic impedances and electrical lengths of the conventional transmission lines . The ATL is easy to design and adjusts electrical parameters and reduces the dimension of circuits significantly, especially at low frequency band. The ATL is useful to achieve various microwave components, such as branch-line couplers , antennas , and baluns . However, there are still some problems to use ATLs for miniaturized circuit design, especially when designing high impedance transmission lines, which limits the application of ATLs. Although several power dividers with artificial transmission lines have been proposed , they did not involve the implementation of high impedance lines.
In this paper, in order to achieve high impedance transmission line, an ATL with double-sided parallel-strip lines (DSPSLs) has been proposed. In order to further miniaturize size of 4 : 1 unequal Wilkinson power divider, other two sections of ATLs are used to take place of conventional microstrip transmission lines. Simulated and measured results agree well with each other and the measurements show good performance.
2. N:1 Unequal Wilkinson Power Dividers
Topology of N:1 unequal Wilkinson power divider is shown in Figure 1, and [R.sub.2], [R.sub.3] are loaded impedances of output ports 2 and 3, while [R.sub.int] is isolation impedance [6-8].
When output power of output port 2 is [k.sup.2] times ([k.sup.2] = N) of port 3, lengths of branch arm 2 and branch arm 3 of power divider are quarter wavelength, respectively, and their characteristic impedances can be expressed as
[Z.sub.2] = [Z.sub.0] [square root of (1 + [k.sup.2]/[k.sup.3])], [Z.sub.3] = [Z.sub.0] [square root of (k (1 + [k.sup.2]))]. (1)
The loaded impedances of output ports [R.sup.2] and [R.sup.3] are calculated as
[R.sub.2] = [Z.sub.0]/k, [R.sub.3] = k[Z.sub.0]. (2)
The isolation impedance [R.sub.int] can be obtained by
[R.sub.int] = [Z.sub.0] 1 + [k.sup.2]/k. (3)
All characteristic impedances of the microstrip lines, isolation resistors, and loads at output ports with respect to N are given in detail in Table 1 with the notations marked in Figure 1.
In actual practice, the loaded resistors [R.sup.2] and [R.sup.3] are, respectively, replaced by impedance transformers with impedances [Z.sub.4], [Z.sub.5] connecting to [Z.sub.0] in order to be implemented and tested easily. Therefore, the topology can be redrawn in Figure 2, and the impedances of [Z.sub.4] and [Z.sub.5] can be determined by
[Z.sub.4] = [Z.sub.0]/[square root of (k)],
[Z.sub.5] = [Z.sub.0]/[square root of (k)] (4)
Consequently, for a practical unequal 4:1 power divider, [Z.sub.4] = 35.4 [OMEGA], [Z.sub.5] = 70.7 [OMEGA], [Z.sub.2] = 39.5 [OMEGA], [Z.sub.3] = 158.1 [OMEGA], and [R.sub.int] = 125 [OMEGA] as shown in Table 1.
3. Theories of ATLs and DSPSLs
3.1. Analysis of ATLs. The concept of ATL was proposed by Wang et al. , which is composed of a series of microstrip meandered-line inductors, parallel-plate capacitors, and interdigital capacitors. The physical structure and lumped-element equivalent circuit of a section of ATL are shown in Figure 3, respectively. Comparing to conventional microstrip transmission lines, using ATLs can achieve much smaller size of microwave components, especially at low frequency band. For a unit of ATL the characteristic impedance [Z.sub.c] and guided wavenumber [[beta].sub.g] can be expressed by
[Z.sub.c] = [square root of ([L.sub.tot]/[C.sub.tot])], [[beta].sub.g] = [omega] [square root of ([L.sub.tot] x [C.sub.tot])], (5)
where [omega] is the operating angular frequency. [L.sub.tot] is the total series inductance of the equivalent lumped inductors, while [C.sub.tot] is the total shunt capacitance of the equivalent lumped capacitors. Therefore, [L.sub.tot] and [C.sub.tot] can be given by
[L.sub.tot] = [L.sub.1] + [L.sub.2] + [L.sub.3],
[C.sub.tot] = [C.sub.l1] + [C.sub.l2] + [C.sub.l3] + [C.sub.l4] + [C.sub.p1] + [C.sub.p2] + [C.sub.p3] + [C.sub.p4] + [C.sub.s1] + [C.sub.s2] + [C.sub.s3] + [C.sub.s4]. (6)
From (5) we can find that when [L.sub.tot] and [C.sub.tot] changed proportionally, only the guided wavenumber [[beta].sub.g] would change while characteristic impedance [Z.sub.0] remains the same value. Consequently, by increasing guided wavenumber [[beta].sub.g], the physical length of demanded microstrip ATL is reduced comparing to structures of conventional microstrip transmission line, especially when operating frequency is in low frequency band.
Based on the above analysis of ALT, the design procedure can be described as follows.
Step 1. From (6), the total series inductance values and shunt capacitance values can be calculated to achieve the required characteristic impedance and phase shift.
Step 2. To extract the equivalent inductance and capacitance values, each element is simulated by the EM full-wave simulation software of IE3D and converted to their corresponding the [pi]- or T-equivalent circuits.
Step 3. The capacitance values can be optimized by tuning the fingers of interdigital capacitors or by adjusting the occupied area of parallel-plated capacitors, while the inductance values can be adjusted by tuning the length or width of meandered-lines. However, the dimensions of the lines still need finetuning when considering parasitic couplings between those elements.
3.2. DSPSLs and Conversion Circuit. DSPSL is balanced transmission line, and its basic structure is constituted of parallel metal transmission lines on both surfaces of the dielectric substrate [9-11]. Its three-dimensional view is shown in Figure 4. In fact, DSPSL can be equivalent to two microstrip lines sharing a common ground plane back to back, and the two microstrip lines have metal strips with the same width. Therefore, the relationship for impedance of DSPSL and microstrip line could be expressed by
[Z.sub.c,DSPSL] = 2[Z.sub.c,MS], (7)
where [Z.sub.c,DSPSL] represents characteristic impedance of DSPSL and [Z.sub.c,MS] is characteristic impedance of microstrip line with the same metal-strip width, half height of dielectric substrate.
When balanced circuit of DSPSL is applied to unbalanced circuit of microstrip transmission line, circularly tapered conversion circuit is used as shown in Figure 5, since circularly tapered metal line on bottom surface is smoother and discontinuity is less than conversion circuits with other shapes. For DSPSL with characteristic impedance of 50 Q, its width is 3.5 mm, while the width of microstrip line is 2.7 mm on a F4B-2 substrate with relative permittivity [[epsilon].sub.r] = 2.65 and height h = 1 mm at the operating frequency of 0.9 GHz. As shown in Figure 6, the simulated results by IE3D software demonstrate that with different radii the performances of circularly tapered conversions are not very different in insertion losses and return losses. Consequently, radius R = 5 mm is chosen for circularly tapered conversion circuit when taking circuit size into consideration. On the occasion, the bandwidth is from 0 GHz to 10.8 GHz, and in the band the insertion loss is less than 0.5 dB while the return loss is more than 19 dB.
3.3. Implementation of High Characteristic Impedance Line. The implementation of 158.1 [OMEGA] line would encounter too narrow line to fabricate if using microstrip transmission line or ATL. To solve the problem, based on the analysis mentioned above, a transmission line of 158.1 [OMEGA] is achieved using DSPSL and ATL as shown in Figure 7. At the two ends of the transmission line, circularly tapered conversions with 5 mm radius are adopted. And the ATLs on the top and bottom surface are perfectly symmetrical without any stagger in the vertical direction.
Simulated s-parameters of proposed 158.1 [OMEGA] transmission line are shown in Figure 8, while simulated impedance is shown in Figure 9. It shows that phase shift is 89.91 degree at the operational center frequency of 0.9 GHz, while [absolute value of [S.sub.11]] = -43.96 dB, [absolute value of [S.sub.21]] = -0.10 dB, Re(Zc) = 158.17 [OMEGA], and Im(Zc) = 0.99 [OMEGA]. It is concluded that the transmission line has good performance for designing components.
4. Circuit Design and Measurements
A full-wave EM simulation software of IE3D is used in performing the design of 4: 1 unequal power divider which has been implemented on a F4B-2 substrate with relative permittivity [[epsilon].sub.r] = 2.65 and height h = 1 mm. The technology combining DSPSL and ATL is applied for designing the transmission line of 158.1 [OMEGA], while other sections of transmission lines are achieved by conventional ATLs or transmission line. As a result, all the optimized specific parameters of ATLs of proposed power divider are shown in Table 2 with the notations marked in Figure 3(a).
The photo of the fabricated unequal power divider is shown in Figure 10, and circuit size is 55.3 mm x 37.8 mm, that is 0.25[[lambda].sub.g] x 0.17[[lambda].sub.g], where [[lambda].sub.g] is guided wavelength
on the substrate at 0.9 GHz. Comparing to a power divider implemented by conventional microstrip lines, the occupied area of fabricated power divider is about 40%.
The simulated and measured results of proposed 4:1 unequal Wilkinson power divider are shown in Figure 11. Figure 11(a) shows that at the center frequency of 0.9 GHz the return loss is nearly 35 dB. The bandwidth is from 0.62 GHz to 1.18 GHz when return loss is more than 10 dB. At 0.9 GHz, the insertion losses of output port 2 and port 3 are 1.17 dB and 7.37 dB, respectively. As shown in Figure 11(b), the return loss of port 2 in the range of bandwidth is above 10 dB and more than 12.4 dB for port 3, proving that the power divider is well matched at output ports. The isolation between output ports 2 and 3 is more than 15.3 dB in the range of bandwidth, as shown in Figure 11(b). Moreover, as shown in Figure 11(c), in bandwidth output differential magnitude ([absolute value of [S.sub.21]] - [absolute value of [S.sub.31]]) is 6.02 dB [+ or -] 0.53 dB, and output differential phase (Ang([S.sub.21]) - Ang([S.sub.31])) is within [+ or -] 5.1 degree. Between 0.62 GHz and 1.18 GHz, the measured power split ratio is close to 4:1 at port 2 and port 3 with excellent impedance matching and isolation, and at 0.9 GHz the power split ratio is 4.17, as shown in Figure 11(d). In conclusion, there is a good agreement between the simulated and measured results, and the measured results demonstrate an excellent performance as 4:1 unequal power divider.
The performance of this proposed power divider (this work) is compared to several previous designs in Table 3. The power divider in this work has similar electrical performance with the other power dividers but with small size, and it totally solves the problem of high impedance line. The power divider proposed in reference  has a similar performance to our work with high impedance of 158.1 [OMEGA], and a very narrow meandered-line with 0.2 mm width is used to approximate to the high impedance. However, by this approach the narrow meandered-line could not realize the transmission line of 158.1 [OMEGA] designed on substrate with higher relative permittivity or thickness, and it could not achieve line with higher impedance. But this proposed method to design high impedance line in this work can design transmission lines with even much higher characteristic impedance.
A miniaturized 4:1 unequal Wilkinson power divider has been designed and experimentally verified adopting ATLs, and 158.1 [OMEGA] transmission line is achieved by using DSPSL and ATL. The proposed design approach of high impedance using DSPSL and ATL can design even much higher impedance lines with compact size and good performance. The proposed power divider using the design approach achieved 4:1 power split ratio at 0.9GHz, with bandwidth from 0.62 Ghz to 1.18 GHz. And in the bandwidth, the power divider shows good performance in return losses, insertion losses, isolations, and so on. These results demonstrate that the miniaturized 4 : 1 power divider is highly suited for wireless communication applications, which require compact structures. And the method combining of ATL and DSPSL has good prospects in designing microwave circuit.
Conflicts of Interest
The authors declare that they have no conflicts of interest.
This work was supported by National Natural Science Foundation of China (61401054) and Scientific and Technological Research Program of Chongqing Municipal Education Commission (KJ1400417).
Wen Huang, Wei Ruan, and Fei Tan
College of Optoelectronic Engineering, Chongqing University of Posts and Telecommunications, Chongqing 400065, China
Correspondence should be addressed to Wen Huang; email@example.com
Received 9 January 2017; Revised 19 March 2017; Accepted 9 April 2017; Published 27 April 2017
Academic Editor: Luciano Tarricone
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Caption: Figure 1: Topology of N:1 unequal Wilkinson power divider.
Caption: Figure 2: Topology of N:1 practical Wilkinson unequal power divider.
Caption: Figure 3: Unit cell of ATL.
Caption: Figure 4: Three-dimensional DSPSL.
Caption: Figure 5: Circularly tapered conversion circuit.
Caption: Figure 6: S-parameters of circularly tapered conversion.
Caption: Figure 7: Proposed transmission line of 158.1 [OMEGA].
Caption: Figure 8: Simulated s-parameters of proposed 158.1 [OMEGA] transmission line.
Caption: Figure 9: Simulated impedance of proposed 158.1 [OMEGA] transmission line.
Caption: Figure 10: Photo of fabricated 4:1 unequal power divider.
Caption: Figure 11: Simulated and measured results of4:1 unequal power divider.
Table 1: Characteristic impedances, isolation resistances, and loads N of an N:1 unequal Wilkinson power divider. N [Z.sub.2] ([OMEGA]) [Z.sub.3] ([OMEGA]) [R.sub.int] ([OMEGA]) 2 51.5 103.0 106.1 3 43.9 131.6 115.5 4 39.5 158.1 125.0 5 36.6 183.1 134.2 6 34.5 2070 142.9 N [R.sub.2] ([OMEGA]) [R.sub.3] ([OMEGA]) 2 35.4 70.7 3 28.9 86.6 4 25.0 100.0 5 22.4 111.8 6 20.4 122.5 Table 2: Dimensions of ATLs of proposed power divider (unit: mm). Impedance [l.sub.1] [l.sub.2] [l.sub.3] [l.sub.4] 158.1 [OMEGA] 1.5 3 7.8 5.5 35.4 [OMEGA] 4 3 13.6 1.5 70.7 [OMEGA] 4.1 2.8 9 4.1 Impedance [l.sub.5] [l.sub.6] [w.sub.1] [w.sub.2] 158.1 [OMEGA] 5.5 7.8 0.6 0.2 35.4 [OMEGA] 1.5 4.5 5.7 0.6 70.7 [OMEGA] 4.2 6.4 1.6 0.4 Impedance [w.sub.3] [w.sub.4] [s.sub.1] [s.sub.2] 158.1 [OMEGA] 0.2 7.4 0.3 1.6 35.4 [OMEGA] 0.6 14.9 1.8 0.6 70.7 [OMEGA] 0.6 8.7 0.7 0.7 Table 3: Performance comparison of 4:1 unequal power divider. [absolute value of Size [S.sub.11]] 15 dB BW (%)  0.13[[lambda].sub.g] x 0.3 0.23[[lambda].sub.g]  0.30[[lambda].sub.g] x 0.5 0.77[[lambda].sub.g] This work 0.17[[lambda].sub.g] x 0.3 0.25[[lambda].sub.g] [absolute value of [absolute value of [DELTA][PHI] [S.sub.21]] (dB) [S.sub.31]] (dB) ([degrees])  1.3 [+ or -] 0.5 7.4 [+ or -] 0.5 [+ or -] 4  1.5 [+ or -] 0.5 7.5 [+ or -] 0.5 [+ or -] 6.1 This work 1.2 [+ or -] 0.4 7.3 [+ or -] 0.5 [+ or -] 5.1 Resistor Solve high number impedance  1 No  3 Yes This work 1 Yes [DELTA][PHI], phase difference.
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|Title Annotation:||Research Article|
|Author:||Huang, Wen; Ruan, Wei; Tan, Fei|
|Publication:||International Journal of Antennas and Propagation|
|Date:||Jan 1, 2017|
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