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A Diagonally Weighted Binary Memristor Crossbar Architecture Based on Multilayer Neural Network for Better Accuracy Rate in Speech Recognition Application.


The neural network architecture is widely used in many research fields such as speech recognition, image recognition, robot control [1-3]. To simulate the neural network architecture on hardware, a large variety of hardware implementation using analog and digital electronics have been performed [4-6]. Here, synaptic weights can be stored in CMOS transistors. However, the transistor size cannot be scaled gradually according to the trend of CMOS transistor number in these chips every year.

In the conventional neural network hardware implementation, the synaptic weighs suffered from the difficulties of updating real-time weights by CMOS transistor characteristics. This is because it costs very huge power consumption for weight storage and nonlinearity in synaptic weight [7]. Moreover, the large scale of the synaptic weighting multiplier is also very limited in hardware implementation due to bottleneck problems. To overcome these problems in the neural network architecture, the new nanotechnologies are researching to exploit this system more compactly such as quantum dots [8] and resonant tunneling diode [9].

In addition, the introduction of the first memristor [10], implemented by Hewlett-Packard lab and completely made in 2008, has opened a new research field in applying the memristor device to neuron networks [11]. Memristor is a memory resistor, which is capable of storing the state after power off. The memristor can be connected as a synaptic weight in the neural network. Memristance can be changed and updated by applying the voltage, current, and timing during the training process of the neural network. In digital circuits, the memristor can achieve either a high-resistance state (HRS) or a low-resistance state (LRS). It means that memristor can store '1' or '0' with the two states. This memristor plays a role as a 2-terminal switch to change the resistance between high resistance state (HRS, logic '0') and low resistance state (LRS, logic '1').

Especially, the memristor-based crossbar architecture has been a promising candidate for future computing system thanks to their low power consumption, high density, and fault tolerance [12-16]. For example, the filamentary switching binary 2M synapse, consisting of M+ memristor crossbar array and M- memristor crossbar array, is easier to be fabricated than analog memristors for speech recognition applications [14]. In comparison, the twin memristor crossbar architecture shows a better recognition rate for pattern recognition than the 2M crossbar array, consisting of plus-polarity and minus-polarity connection [15]. To reduce the array circuit size, the memristor-based crossbar array architecture has been presented with fewer memristors and transistors. Here, both plus-polarity and minus-polarity connection matrices are realized by a single crossbar and a simple constant-term circuit, thus, reducing the physical size and power dissipation [15-16]. However, these methods have been limited to a single layer neural network in fundamental processing tasks of binary and gray-scale images. The large-scale processing tasks in functionality and hardware implementation are desired.

The multilayer neural network has been proposed for extending the single layer network to the higher dimension and more complex tasks of multiprocessing [17-20]. The multilayer neural network is able to process the cascaded duties for image segmentation, skeletonization, halftoning, and so on [17]. Thus, the mathematical model analysis and algorithm design have been researched in theory as well as in hardware implementation of FPGA platforms, which is essential for real applications [18]. Moreover, the artificial synapse connections in multilayer neural networks are implemented on-chip using memristor bridge synapse, consisting of multiple identical memristors that are arranged in a bridge-like architecture [19-20]. The bridge memristor synapse circuit can create both positive and negative weight values that can be implemented easily a neuromorphic system in hardware. The memristor-based multiplayer with online gradient descent training was proposed using single memristor and two CMOS transistor per one synapse [21]. A memristor-based single-layer neural network is expanded into a multiplayer neural network [22]. Here, a memristor-based AND logic switch is utilized to update synaptic crossbar circuit by an adaptive backpropagation algorithm, which causes area and power overhead and suffers from nonlinear characteristics of programming memristor [22]. A memristor crossbar circuit, acting as the synapse, which realizes the signed synaptic weights, was proposed for memristive multilayer neural network [23].

In addition, many researchers have used these binary memristor crossbars for the multilayer neural network model in speech recognition applications, which are based on matching audio inputs and synaptic weights [14-15]. However, this is not accurate if the input signal is unstable or voice samples come from various people. If the test sample is best matched with the trained sample, the output is the biggest. Nevertheless, the test voice is not entirely the same as the trained sample due to accent and dialect problems. Thus, the comparison results are not certainly reliable based on the signal comparison. The signal comparison technique that was applied to the conventional memristor crossbar architecture achieves lower recognition rate compared to the neural network technique that is applied to the diagonally weighted binary memristor crossbar architecture. The proposed technique is built from the expressions of binary digit multiplication and summation in the neural network model equations, which is more accurate than the conventional signal comparison technique.

In this paper, we propose the diagonally weighted binary crossbar array in the multilayer neuron network model, including M+ and M- memristor arrays corresponding to positive and negative weights, respectively. Depending on the input bits, the memristors are arranged in a diagonal format to generate the structure corresponding to the expressions of the neural network model. In addition, the statistical simulations are discussed and finally summarized.


The neural network model for speech recognition application consists of two main processes that are weight installation and recognition process. First, in the weight installation, the voice input is processed and trained in a neural network model. This weight is quantized into m bits. The obtained bits are stored into the binary memristor. Second, in the recognition process, the voice input is processed and applied to a weighted memristor array to determine outputs.

In the first process, the features are extracted from the voice signal by the Mel frequency cepstral coefficients (MFCC) method, including the steps of pre-processing, framing, windowing, DFT, and Mel frequency log [24]. After that, they are trained in a neural network model by Matlab software. The output is '1' for vowel that is trained else the output is '0'. The recognition process is performed in each sound. In the recognition process, the input is quantized into n bits. The input is normalized for training. After the training process for each vowel, we have 48 weights correspondingly. The weights are adjusted proportionally to the corresponding coefficient, then quantized into n bits. The bits 1 and 0 are stored in two memristors with memristance values of [R.sub.on] and [].

The previous researches have proposed crossbar architecture for speech recognition based on the signal comparison. This is not accurate if the input signal is unstable or the voice samples come from various people. If the test sample is best matched with the trained sample, the output is the biggest. Figure 1(a) shows the data input is '0011'. We have 4 columns that are the weights. The first column is '1111', the second column is '0111', the third column is '1001' and the fourth is '0011'. Here, the black square input represents the high-logic level ('1') while the white square input represents the low-logic level ('0'). The black circle memristor represents the low resistance state while the white circle memristor represents the high resistance state.

In Figure 1(b), the fourth column is the best-matched column with the input vector of '0011'. The number of matched cells is as large as 4 in the fourth column. By summing the results from cells in [M.sup.+] and [M.sup.-] arrays, we can find the best-matched cells as illustrated in Figure 1(b). Hence, we determine the best-matched column with the input vector among four columns.

However, the test voice is not entirely same as the trained sample. Thus, the comparison results are not certainly reliable. For example, in Figure 2, the data input is '0111' as 7, having 4 columns, the first is '1000' as 8, the second '0001' as 1, the third is '0100' as 4 and the last column is '1111' as 15. The data input is 7 nearly equal to the first column that is 8. However, we apply the conventional memristor crossbar architecture to the first column, the result is 0 as a bad expectation. The output of the first column is 0 although the data input is nearly the same as the first column. Thus, the conventional architecture is the reason that causes a low recognition rate. In addition, we cannot recognize a lot of samples from different people with this architecture because each person has a private speech. Therefore, to raise the recognition rate with various human speeches, we propose a new memristor crossbar architecture that is based on the neural network model. Each input is multiplied with each weight. Summation of multiplication results is the output value.

Figure 3 shows the basic neural network model as follows: a set of inputs connects to the hidden layer neurons and these hidden layer neuron outputs connect to the output layer neurons. The output layer neurons are calculated from the input according to the following expressions:

[mathematical expression not reproducible] (1)

[z.sub.q]= log sig([net.sub.q]) (2)

[mathematical expression not reproducible] (3)

Where [x.sub.j] is the input. The [v.sub.j] is hidden layer weight. The [b.sub.q] is the threshold of the hidden layer. The activation function is logsig. The [w.sub.q] is the weight in the output layer. The b.sub.i is the threshold of the output layer.

Based on the above expressions, we propose a new crossbar architecture that includes memristors acting as the weights multiplied with the inputs. As the result, a novel binary memristor crossbar architecture based on the neural network model is presented. Each data input is multiplied with each weight. To multiply the input and the weight, the memristors are arranged as in Figure 4. In Figure 4(a) and 4(b), the data input is '0111'. The row weights are '0101' as 5 and '1101' as 13. This work is similar to the multiplication of two 4-bit binary numbers. Since then, we have 7 columns according to 7 significant position factors 1, 2, 4, 8, 16, 32 and 64, respectively. In Figure 4(a), the result is 7*13 = 91. In Figure 4(b), the result is 7*5 = 35. These results show that if b < c then a*b < a*c as the result of multiplying two integer numbers. In Figure 4(c), the data input is '1101' as 13 and the weight is '0111' as 7. The result is 13*7 = 91 that is the same as the result of Figure 4(a). These results show that a*b = b*a. This is an interchange between two integer numbers.

In Figure 5(a) and 5(b), each weight is divided into two parts that are [M.sup.+] and [M.sup.-] array. If we subtract [M.sup.-] from [M.sup.+], we get either the positive or negative weight, correspondingly. The input is multiplied with these weights. In Figure 5(a), the input is '11' as 3 and the weight is '01' as -1, so the result is -3. Similarly, in Figure 5(b), the input is 3 and the weight is +1, so the result is 3. Hence, these results show that the new memristor crossbar architecture operates like a neural network model. This is satisfied with Eq. (1).

Figure 6 shows the circuit simulated by Eq. (2). The logsig function circuit is designed with input [V.sub.p] and [V.sub.n]. Here, [V.sub.n] is the inverted [V.sub.p]. [V.sub.dc] is added to increase the threshold value. The simulation result of this logsig function is shown in Figure 7.

The activation function is logsig. The expression of logsig function is:

g(x) = 1/1 + [e.sup.-x] (4)

[mathematical expression not reproducible]



Our research focuses on recognizing five vowels: 'a', 'e', 'i', 'o' and 'u' from the human voice. To do this, first, features are extracted from the voice signal by MFCC. There are 48 feature values. Then, they are trained by the neural network model to recognize five vowels. After training, the input layer weights are quantized into n bits and the output layer weights are quantized into m bits. These weight values are stored in a binary memristor crossbar array. By doing so, we can recognize each vowel by multiplying the input signal and the stored weight in binary memristor. The summation of the multiplication results, which is the biggest output among five outputs, represents the input signal.

The features are extracted from voice signal by MFCC method including the steps such as pre-processing, framing, windowing, DFT, and Mel frequency log. Then, they are trained in a neural network model by MatLab. The neural network model has five neurons in the hidden layer, the transfer function is logsig. The output is '1' for vowel if it is trained else the output is '0'. The input is quantized into p bits with [2.sup.p] levels. The training input values are normalized in the range from -1 to 1. In this case, we choose p = 2. After the training process for each vowel, we have 2 x 48 x 5 weights in the input layer and 5 x 5 weights in the hidden layer respectively. The weights are quantized into two bits in the input layer and two bits in the hidden layer. The bits 1 and 0 are stored in two memristors with memristance values of [R.sub.on] and [], respectively. The multilayer neural network model includes 48 inputs, five neurons in the hidden layer, and five outputs. The activation function is the logsig in the hidden layer and linear in the output layer.

The Figure 8 shows the proposed binary memristor crossbar in the neural network model. We have 48 input channels, five column groups from [V.sub.1] to [V.sub.5] corresponding to five neurons in the hidden layer. There are six columns in each column group that is divided into [M.sup.+] and [M.sup.-] array, respectively. The memristors are arranged diagonally to determine the signed weight values. Each column in the [M.sup.+] or [M.sup.-] array has a significant position factor correspondingly. In the order from the left to the right, it is 4, 2 and 1, respectively. Next, three subtraction circuits determine the output after subtracting [M.sup.-] from [M.sup.+]. Then, three multiplier circuits that are corresponding to three position factors 4, 2 and 1, are calculated to recover the value of the multiplication between the inputs and the weights. Finally, an adder circuit adds three multiplier circuit outputs to the threshold voltage value. The [Z.sub.1] adder output is the value of Eq. (1). Thus, we describe the net value by using new binary memristor crossbar architecture. Next, an activation function circuit is proposed to describe Eq. (2). Similarly, the weights are quantized into two bits in the output layer and arranged in horizontal rows. The network output is generated by a group of two subtraction circuits, two multiplier circuits with 2 position factors that are 2 and 1, and an adder circuit.

Figure 9(a) shows the schematic of the proposed binary memristor crossbar circuit in detail. The circuit has 48 input channels, 2-bit binary in each channel, and each 2-bit binary weight stored into each row. The 2-bit weight is set up by four memristors. Each row has four memristors in each column group. Another row is shifted left to create six columns. These two rows are divided into two parts that are programmed either positive or negative weights. R.sub.g is used to get voltage instead of current. There are [V.sup.+.sub.1,4], [V.sup..sub.1,2], [V.sup.+.sub.1,1], [V.sup.-.sub.1,4], [V.sup.-.sub.1,2] and [V.sup.-.sub.1,1] for the first column group [V.sub.1]. Figure 9(b) shows a subtraction circuit, which is used to subtract [M.sup.-] from [M.sup.+]. We have [H.sub.1,4] = [V.sup.+.sub.1,4] - [V.sup.-.sub.1,4] with [R.sub.1] = [R.sub.2] = [R.sub.3] = [R.sub.4]. Similarly, we get [H.sub.1,2] and [H.sub.1,1].

Figure 9(c) shows a multiplier circuit. The multiplier output is calculated by [G.sub.1,4] = (1 + [R.sub.6]/[R.sub.5])[H.sub.1,4] corresponding to the multiplier factor of 4. Here, [R.sub.6] = [3R.sub.5]. Similarly, we have [G.sub.1,2] and [G.sub.1,1] with [R.sub.6] = [R.sub.5] and [R.sub.6] = 0. Figure 9(d) shows an adder circuit that [b.sub.1,1] is threshold voltage. We have [S.sub.1] = [G.sub.1,1] + [G.sub.1,2] + [G.sub.1,3] + [b.sub.1,1]. Therefore, [S.sub.1] is a net in Eq. (1). Figure 9(e) is an activation function circuit. The activation function output is [Z.sub.1] as seen in Eq. (2). Thus, the design meets requirements of circuit characteristics in the input layer. We have five values [Z.sub.1], [Z.sub.2], [Z.sub.3], [Z.sub.4] and [Z.sub.5] corresponding to five neurons in the hidden layer.

We have another memristor crossbar subtraction circuit in a role as the hidden layer weight. Similarly, we have a multiplier circuit and an adder circuit that work the same way the input layer does. The outputs are charged up by the capacitors [C.sub.a], [C.sub.e], [C.sub.i], [C.sub.o], and [C.sub.u]. Here, the five capacitors [C.sub.a], [C.sub.e], [C.sub.i], [C.sub.o], and [C.sub.u] are represented to the five vowels 'a', 'e', 'i', 'o', and 'u'.

The fastest charged capacitor among the five capacitors [C.sub.a], [C.sub.e], [C.sub.i], [C.sub.o], and [C.sub.u] determines a certain vowel corresponding to the input of a human voice.

The capacitor [C.sub.a] can be charged up by the weight summation [VC.sub.a]. If the weight summation of [VC.sub.a] is large, [C.sub.a] can be charged to [V.sub.CC] very fast. If the weight summation of [VC.sub.a] is small, it takes a longer time to charge [C.sub.a] to [V.sub.CC]. This is shown in Figure 10. Then [VC.sub.a], [VC.sub.e], [VC.sub.i], [VC.sub.o], and [VC.sub.u] are compared with a reference voltage [V.sub.ref] through the comparator [I.sub.1], [I.sub.2], [I.sub.3], [I.sub.4], and [I.sub.5] as shown in Figure 9(m). If [VC.sub.a] is bigger than [V.sub.ref], [D.sub.a] becomes high. In the other hands, [VC.sub.e], [VC.sub.i], [VC.sub.o], and [VC.sub.u] are smaller than [V.sub.ref], the outputs of [D.sub.e], [D.sub.i], [D.sub.o], and [D.sub.u] become low. [G.sub.1], [G.sub.2], [G.sub.3] are the OR gates. A delay time [tau] between [G.sub.4] and [G.sub.5] creates a small CLK pulse. [FF.sub.a], [FF.sub.e], [FF.sub.i], [FF.sub.o], and [FF.sub.u] are flip flops with inputs [D.sub.a], [D.sub.e], [D.sub.i], [D.sub.o], and [D.sub.u]. The simulation waveforms [VC.sub.a] [VC.sub.e], [VC.sub.i], [VC.sub.o], and [VC.sub.u] are shown in Figure 10. Here, [VC.sub.a] seems to be charged to [V.sub.CC] faster than the other capacitor nodes [VC.sub.e], [VC.sub.i], [VC.sub.o], and [VC.sub.u]. So, the vowel 'a' is the best among the other vowels. Then, all capacitors will be discharged in the next pulse to prepare for testing the next input.

The timing diagram shows the important signals in Figure 11. When the CLK signal is high, all the capacitor nodes [VC.sub.a], [VC.sub.e], [VC.sub.i], [VC.sub.o], and [VC.sub.u] are charged to [V.sub.CC]. At this time, [VC.sub.a] [VC.sub.e], [VC.sub.i], [VC.sub.o], and [VC.sub.u] are higher than [V.sub.ref]. Thus, [D.sub.a], [D.sub.e], [D.sub.i], [D.sub.o], and [D.sub.u] are at high level. If [C.sub.a] is charged to [V.sub.CC] faster than [C.sub.e], [C.sub.i], [C.sub.o], and [C.sub.u], [VC.sub.a] gets a higher voltage level among [VC.sub.a], [VC.sub.e], [VC.sub.i], [VC.sub.o], and [VC.sub.u]. If [VC.sub.a] becomes higher than [V.sub.ref], the [D.sub.a] becomes high. So, [D.sub.a] can also be the fastest rising signal among [D.sub.a], [D.sub.e], [D.sub.i], [D.sub.o], and [D.sub.u]. Because the [D.sub.a] generates the locking pulse that is the clock signal of D flip-flop circuits [FF.sub.1], [FF.sub.2], [FF.sub.3], [FF.sub.4], and [FF.sub.5], the [FF.sub.1] register leads to a high-level output signal. Therefore, we can determine this vowel is similar to the voice input. The [D.sub.a] signal makes [Output.sub.a] high-level and the other output signals become low-level as shown in Figure 11.

Table I shows the number of memristors used and the average recognition rate corresponding to the number of the input bits, the input layer weight bits, and the hidden layer weight bits. A statistical table shows the input bits are in the range from 1 to 5. The weight bits in the input layer are from 2 to 4 and the weight bits in the hidden layer are used as 2. Based on the statistics table, realized that the first row has a good recognition rate using just a few bits. Here, the input uses one bit, the input layer weight uses two bits, and the hidden layer uses two bit. The result is compared with the previous research [15] that shows the recognition rate increases from 89.6% to 94% while reducing the used memristor hardware up to more than 50%. Here, the proposed circuit consumes 1010 memristors while the conventional scheme does 2560 memristors.

Figure 12 shows the statistical distribution according to the memristance variation. The memristances of 1M[ohm] HRS and 10K[ohm] LRS have a standard deviation (= [sigma]) of 10%. The statistical variation is measured by Monte Carlo simulation. The Monte Carlo simulation estimates tolerant of recognition rate when memristance variation is in the range 1% to 15%. In Figure 13, the recognition rate of the proposed binary memristor crossbar decreases a little bit, only from 94% to 93.7% while the memristance variation increases from 1% to 15%.


We proposed the diagonally weighted binary memristor crossbar architecture based on the multilayer neural network model for a better accuracy rate in the speech recognition application. The proposed crossbar architecture acts as a binary multiplier circuit between the inputs and the weights in a neural network model. The signed weights are stored in binary memristor arrays. Combined with the activation function, the proposed circuit is implemented to describe the speech recognition application for 5 vowels. Based on the input bit numbers from 1 to 5, the weight bit number in the input layer from 2 to 4 and the weight bit number in the hidden layer as 2, the memristor number increases from 1010 to 9650 and the recognition rate increases from 94% to 96.6% in 1000 tested samples. The recognition rate of the binary memristor crossbar decreases slightly from 94% to 93.7%, while variation in the memristance fluctuates from 1% to 15%.


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Minh-Huan VO

Ho Chi Minh City University of Technology and Education 01 Vo Van Ngan, Thu Duc District, Ho Chi Minh City, Viet Nam

Digital Object Identifier 10.4316/AECE.2019.02010

         # bits in  # bits in   #           Average
# input  the input  the hidden  memristors  recognition
bits     layer      layer                   rate (%)

1        2          2           1010        94
2        2          2           1970        94.8
3        2          2           2930        95.6
4        2          2           3890        95.4
4        3          2           5810        95.6
5        2          2           4850        95.4
5        3          2           7250        96
5        4          2           9650        96.6
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Author:Vo, Minh-Huan
Publication:Advances in Electrical and Computer Engineering
Date:May 1, 2019
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