# A Controllable Constant Power Generator in 0.35 [micro]m CMOS Technology for Thermal-Based Sensor Applications.

1. IntroductionThe circuit which generates constant power for variable resistive loads finds application in various types of thermal-based sensors, such as mass flow meters, anemometers [1], AC power meters, gas monitoring [2, 3], plant water status monitoring [4], seepage meters [5], and other flowmeters intended for very slow fluids. Thermal-based flow sensors are very attractive because of their simple construction. They basically consist of constant power generator and sensing element. The surrounding fluid transfers heat to/from sensing element depending on its flow rate. As the temperature of the sensing element is changed, its resistance is changed, and the constant power generator changes the voltage drop across the sensing element to keep constant power. Measuring the voltage change across the sensing element, it is possible to extract the information about the fluid flow rate. So, the quality of the constant power generator as a part of the thermal-based sensor is very important. Controllable constant power generator is the circuit which generates constant power dissipation over a range of resistive loads. The control of the generated power is provided by control voltage or control current. The range of resistive loads has to be as large as possible for the particular generated power. In that sense, the quality of constant power generators is determined by the load resistance dynamic range, defined as the ratio of the largest load resistance to the smallest load resistance ([[R.sub.L].sub.max]/[[R.sub.L].sub.min]), for the particular value of dissipated power. The other important characteristic of the constant power generator is the value of generated power for a given load resistance, depending on specific application. The relative error of generated power over the range of load resistance is the key quality parameter of the constant power generator. Low-supply voltage of constant power generator is critical for many applications as a consequence of the general trend in electronics. The ratio of the largest voltage drop across the resistive load and supply voltage ([[V.sub.L].sub.max]/[V.sub.DD]) can be used as a quality indicator of constant power generators. One of the main problems in constant power generator design is its stability caused by feedback loops.

There are several designs of constant power generators, developed mostly in BiCMOS and bipolar technologies. A CMOS controllable constant power generator based on the resistive mirror [1] has the range of generated power from 0.48 mW to 10.8 mW, and the load resistance dynamic range up to 28, with the relative error of generated power less than 2.2% and the supply voltage of 10 V. The constant power generator presented in [1] uses four operational amplifiers OP97 which are designed in a complementary bipolar technology, while the rest of the circuit is realized using n-channel MOSFETs. Hence, the circuit [1] can be considered as a BiCMOS technology design. The controllable constant power generator [3], based on CMOS translinear loop, has a load resistance range from 470 u to 1.47 ku and is able to generate power up to 11 mW, with the supply voltage of [+ or -]5 V and the relative error of generated power up to 3%. The circuit presented in [3] uses off-chip operational amplifier L[M.sub.30]1 designed in a complementary bipolar technology, while the rest of the circuit is realized in a CMOS technology. Hence, the circuit [3] can be considered as a BiCMOS technology design. Controllable constant power generator [4-6] can change the dissipated power by a factor of 1: 1000, using the log-antilog circuit with bipolar junction transistors. This controllable constant power generator uses eight OPA4227 operational amplifiers designed in a complementary bipolar technology. Consequently, the circuit [4-6] can be considered as a bipolar technology design. The controllable constant power generator [7] in BiCMOS technology achieves load resistance range of 1 : 50, with generated power up to 100 mW. The microcontroller-based solution [9] can achieve large resistance dynamic range and large power dynamic range, but at the price of reduced frequency bandwidth. The CMOS design proposed in [10] for small variations of the resistive load has a large relative error of the generated power.

Taking into account that the existing designs of controllable constant power generators are designed mostly in BiCMOS and bipolar technologies and that CMOS technology is the most popular and the cheapest technology so far, the goal of this work is the design of fully integrated controllable constant power generator in a pure CMOS technology. This paper presents controllable constant power generator in 0.35 [micro]m CMOS technology based on current-mode multiplier/divider circuit [8]. The generated power can be adjusted by two control currents which are the input currents of the multiplier/divider circuit. Through the detailed analysis and simulations, it is shown that proposed design is able to generate constant power over a large range of the load resistance. The mathematical model for the loop gain of the controllable constant power generator shows that circuit has no stability problems for a wide range of resistance for the particular generated power. The influence of the process parameter variations and the temperature variations to the proposed design is also analyzed.

2. Circuit Description

2.1. Basic Principle. The main purpose of the constant power generator is to maintain the constant power dissipation across the resistive load:

[P.sub.L] = [I.sub.L][V.sub.L] = const, (1)

where [P.sub.L] is the generated power across the resistive load, [I.sub.L] is the current flowing through the resistive load, and [V.sub.L] is the voltage across the resistive load. Generated power has to be independent of the load resistance. Also, it is desirable to have the possibility to control generated power easily.

The basic principle of the controllable constant power generator with a novel method for achieving a constant power dissipated on the resistive load is shown in Figure 1. It consists of multiplier/divider circuit, second generation current conveyor (CCII), load resistor [R.sub.L], reference resistor [R.sub.REF], and two DC current sources [I.sub.1] and [I.sub.2]. The output current IL of the multiplier/divider circuit is flowing through the resistive load [R.sub.L]. The voltage [V.sub.L] across the resistive load is transferred via CCII to the resistor [R.sub.REF]. So, the output current [I.sub.3] of the CCII is given by

[I.sub.3] = [V.sub.L]/[R.sub.REF]. (2)

On the other hand, the output current of the multiplier/ divider circuit is given by

[I.sub.L] = [I.sub.1][I.sub.2]/[I.sub.3]. (3)

So, the generated power [P.sub.L] can be expressed as

[P.sub.L] = [I.sub.L][V.sub.L] = [R.sub.REF][I.sub.1][I.sub.2] = const. (4)

The generated power is independent of the load resistance [R.sub.L] and can easily be adjusted by changing control currents [I.sub.1] and/or [I.sub.2].

2.2. Complete Circuit Schematic. The multiplier/divider circuit [8] is shown in Figure 2. It is based on the CMOS translinear principle. The circuit can be divided into two parts. The first part gives the current which is proportional to the square root of the product of two input currents (geometric mean) at its output. The second stage performs squarer/ divider operation. The MOSFETs [M.sub.1], [M.sub.2], [M.sub.3], [M.sub.4], [M.sub.1a], [M.sub.2a], [M.sub.3a], and [M.sub.4a] have long enough channels of 3 f m, so the channel length modulation effect can be neglected in the analysis. Assuming a good enough matching of MOSFETs forming the translinear loops ([V.sub.t1] = [V.sub.t2] = [V.sub.t3] = [V.sub.t4], [V.sub.t1a] = [V.sub.t2a] = [V.sub.t3a] = [V.sub.t4a], [[beta].sub.1] = [[beta].sub.2] = [[beta].sub.3] = [[beta].sub.4], and [[beta].sub.1a] = [[beta].sub.2a] = [[beta].sub.3a] = [[beta].sub.4a]) and a simple quadratic model for the drain current of the MOSFET operated in the saturated region, it can be shown [8] that the output current IL of the multiplier/divider circuit is given by

[I.sub.L] = [I.sub.1][I.sub.2]/[I.sub.3]. (5)

The second-order effects of the multiplier/divider circuits, such as channel length modulation effect and the threshold voltage mismatching effect, are analyzed in [8]. It is stated that the channel length modulation effect can be neglected for the long channel MOSFETs. On the other hand, the threshold voltage mismatching effect could affect the performances of the multiplier or divider circuit, assuming that the multiplier and divider are analyzed separately. On the other hand, if the multiplier and divider are used simultaneously within the multiplier/divider circuit, the threshold voltage mismatching effect is compensated [8]. The body effect of the n-channel MOSFETs in a real n-well CMOS implementation can be solved using n-channel MOSFETs with their own p-wells assuming a twin well technology.

The complete circuit schematic of the proposed controllable constant power generator with a novel method for achieving a constant power dissipated on the resistive load is shown in Figure 3. The output current of the multiplier/ divider circuit is flowing through the resistive load [R.sub.L]. The current [I.sub.3] is obtained as the output current of the CCII. The voltage [V.sub.L] across the resistive load [R.sub.L] is transferred via input stage of the CCII, so the current at terminal X of this CCII is [V.sub.L]/[R.sub.REF]. The differential input stage of the CCII is formed by the MOSFETs [M.sub.12] and [M.sub.13], with the active cascoded load (MOSFETs [M.sub.14], [M.sub.15], [M.sub.16], and [M.sub.17]). The differential input stage is biased by MOSFET [M.sub.11] and biasing voltage [VB.sub.3]. The output current is transferred by the two output cascoded current mirror (MOSFETs [M.sub.18], [M.sub.19], [M.sub.20], [M.sub.21], [M.sub.22], and [M.sub.23]). So, the current at the output of the CCII is [I.sub.3] = [V.sub.L]/[R.sub.REF]. To change the direction of the current [I.sub.3], the wide-swing current mirror is used. This current mirror consists of MOSFETs [M.sub.24], [M.sub.25], [M.sub.26], and [M.sub.27] and biasing voltage [V.sub.B4]. The current IL flowing through the resistive load [R.sub.L] is mirrored by the current mirror formed by the MOSFETs [M.sub.6a], [M.sub.8a], [M.sub.9], and [M.sub.10]. The current mirror formed by the MOSFETs [M.sub.28], [M.sub.29], [M.sub.30], and [M.sub.31] is used to sum currents [I.sub.3] and IL and to divide the sum of the currents by four. In that aim, the channel widths of the MOSFETs [M.sub.28] and [M.sub.30] are four times larger than the channel widths of the MOSFETs [M.sub.29] and [M.sub.31]. The direction of the resulting current is changed using the cascoded current mirror formed by MOSFETs [M.sub.32], [M.sub.33], [M.sub.34], and [M.sub.35].

DC current source [I.sub.1] ([I.sub.2]) is realized by using CCII. Its differential input stage is formed by the MOSFETs [M.sub.37] and [M.sub.38] ([M.sub.50] and [M.sub.51]), with the active cascoded load MOSFETs [M.sub.39], [M.sub.40], [M.sub.41], and [M.sub.42] ([M.sub.52], [M.sub.53], [M.sub.54], and [M.sub.55]). The differential input stage is biased by MOSFET [M.sub.3]6 ([M.sub.4]9) and biasing voltage [VB.sub.3]. The current at terminal X of this CCII is [V.sub.C1]/[R.sub.1] ([V.sub.C2]/[R.sub.2]), and it is multiplied by the factor of eight by the two output cascoded current mirror MOSFETs [M.sub.43], [M.sub.44], [M.sub.45], [M.sub.46], [M.sub.47], and [M.sub.48] ([M.sub.56], [M.sub.57], [M.sub.58], [M.sub.59], [M.sub.60], and [M.sub.61]). So, the output current of this current source is [I.sub.1] = 8[V.sub.C1]/[R.sub.1] ([I.sub.2] = 8[V.sub.C2]/[R.sub.2]). To change the direction of the current [I.sub.2], the wide-swing current mirror is used. This current mirror consists of MOSFETs [M.sub.62], [M.sub.63], [M.sub.64], and [M.sub.65] and biasing voltage [V.sub.B4]. The current mirror formed by MOSFETs [M.sub.66], [M.sub.67], [M.sub.68], and [M.sub.69] is used to sum currents [I.sub.1] and [I.sub.2] and to divide the sum of the currents by four. In that aim, the channel widths of the MOSFETs [M.sub.66] and [M.sub.68] are four times larger than the channel widths of the MOSFETs [M.sub.67] and [M.sub.69]. The direction of the resulting current is changed using cascoded current mirror formed by MOSFETs [M.sub.70], [M.sub.71], [M.sub.72], and [M.sub.73].

The generated power of the proposed controllable constant power generator is given by

[P.sub.L] = 64[[V.sub.C1]/[R.sub.1][[V.sub.C2]/[R.sub.2]][R.sub.REF]. (6)

3. Stability Analysis

Controllable constant power generators usually suffer from stability problems [1, 3]. The range of resistive loads and the range of generated power are often reduced as a consequence of this problem [1, 3]. The stability analysis of the proposed controllable constant power generator is performed through the derivation of the loop gain A[beta](s). In the small-signal analysis, the CCII, whose voltage input Y is connected to the active terminal of the resistive load (the output of the multiplier/divider circuit), is modelled as shown in Figure 4 [11, 12]. Capacitance [C.sub.X] is the input capacitance at terminal X of the CCII, resistance [R.sub.X] is the input resistance at terminal X of the CCII, capacitance [C.sub.Y] is the input capacitance at terminal Y of the CCII, capacitance [C.sub.Z1] is the output capacitance at terminal [Z.sub.1] of the CCII, resistance [R.sub.Z1] is the output resistance at terminal [Z.sub.1] of the CCII, capacitance [C.sub.Z2] is the output capacitance at terminal [Z.sub.2] of the CCII, and resistance [R.sub.Z2] is the output resistance at terminal [Z.sub.2] of the CCII. The terminal X of the CCII is connected to the active terminal of the resistor [R.sub.REF]. The terminal Y of the CCII is connected to the active terminal of the resistive load [R.sub.L]. The terminal [Z.sub.1] of the CCII is connected to the source of the MOSFET [M.sub.2a], and the terminal [Z.sub.2] of the CCII is connected to the drain of the MOSFET [M.sub.9]. Current mirrors within multiplier/divider circuit are modelled as simple ones.

The loop gain A[beta](s) of the proposed controllable constant power generator is given by

where the zeroes [[omega].sub.zi] and the poles [[omega].sub.pi] are

[[omega].sub.Z1] = 1/[R.sub.REF][C.sub.X], (8)

[[omega].sub.Z2] = [g.sub.m4a]([C.sub.Z2] - [C.sub.4]) + ([g.sub.m28] + [1/[R.sub.Z2]])[C.sub.1]/[C.sub.1]([C.sub.Z2] + [C.sub.4]), (9)

[[omega].sub.p1] = 1/[R.sub.L]([C.sub.Y] + [C.sub.3]), (10)

[[omega].sub.p2] = 1/([R.sub.X][R.sub.REF]/([R.sub.X] + [R.sub.REF]))[C.sub.X], (11)

[mathematical expression not reproducible], (12)

where [g.sub.m1a], [g.sub.m2a], [g.sub.m3a], [g.sub.m4a], [g.sub.m28], and [g.sub.m34] are the transconductances of the saturated MOSFETs [M.sub.1a], [M.sub.2a], [M.sub.3a], [M.sub.4a], [M.sub.28a], and [M.sub.34a], respectively, [C.sub.1] is the parasitic capacitance at the drain of the MOSFET [M.sub.4a], [C.sub.2] is the parasitic capacitance at the gate of the MOSFET [M.sub.1a], [C.sub.3] is the parasitic capacitance at the drain of the MOSFET [M.sub.6a], and [C.sub.4] is the parasitic capacitance at the drain of the MOSFET [M.sub.9]. It is calculated that the DC loop gain ranges from [absolute value of (A[beta](s = 0))][approximately equal to]0.01, for the lower limit of the resistive loads, to [absolute value of (A[beta](s = 0))][approximately equal to]0.3, for the upper limit of the resistive loads, for appropriate generated powers. The parasitic capacitances [C.sub.1], [C.sub.2], [C.sub.3], and [C.sub.4] are in the order of 1 pF, while the parasitic capacitances [C.sub.X], [C.sub.Y], [C.sub.Z1], and [C.sub.Z2] are in the order of 100 fF. The transconductances of saturated MOSFETs are calculated as [g.sub.mi] = [(2[[beta].sub.i][I.sub.Di]).sup.1/2].

The absolute value of the loop gain frequency characteristic [absolute value of (A[beta](j[omega]))], for the lower limit of the resistive loads and for the appropriate generated powers, is shown in Figure 5. The frequency of the first zero [[omega].sub.z1] is about 150 MHz, the frequency of the next pole [[omega].sub.p2] is about 200 MHz, the frequency of the next pole [[omega].sub.p1] is between 300 MHz and 400 MHz, the frequency of the next pole [[omega].sub.p3] is in the order of 10 GHz, and the frequency of the last zero [[omega].sub.z2] is in the order of 100 GHz. The absolute value of the loop gain frequency characteristic A[beta](j[omega]), for the upper limit of the resistive loads and for the appropriate generated powers, is shown in Figure 6. The frequency of the first pole [[omega].sub.p1] is between 30 MHz and 130 MHz, the frequency of the next zero [[omega].sub.z1] is about 150 MHz, the frequency of the next pole [[omega].sub.p2] is about 250 MHz, the frequency of the next pole [[omega].sub.p3] is in the order of 10 GHz, and the frequency of the last zero [[omega].sub.z2] is in the order of 100 GHz. As the absolute value of the loop gain frequency characteristic [absolute value of (A[beta](j[omega]))] never reaches the value of 0 dB, the system is stable.

4. Simulated Results

The circuit is designed and simulated using PSpice with BSI[M.sub.3] version 3.1 transistor model for TSMC 0.35 gm nwell CMOS process obtained by MOSIS. The circuit is single supplied by [V.sub.DD] = 5 V. Biasing voltages have the following values: [V.sub.B1] = 3V, [V.sub.B2] = 3.1 V, [VB.sub.3] = 0.8 V, and [V.sub.B4]=1.9V. Resistances have the following values: [R.sub.1] = 8 k[ohm], [R.sub.2] = 8 k[ohm], and [R.sub.REF]= 1.25 k[ohm].

The current IL flowing through the resistive load as a function of the voltage [V.sub.L] across the resistive load, for the generated power [P.sub.L] = 5 mW, is shown in Figure 7. The resistance [R.sub.L] is changed from 400 u to 2.2 k[ohm]. Larger values of the voltage across the resistive load (corresponding to larger resistive load) are out of the input voltage range of the CCII, whose input is connected to the active terminal of the resistive load, for a given supply voltage. For larger values of the current flowing through the resistive load (corresponding to smaller resistive load), the multiplier/divider circuit shows larger errors caused by the channel length modulation of the MOSFET [M.sub.1a]. The current [I.sub.L] flowing through the resistive load increases rapidly with the decrease of the resistive load [R.sub.L] due to square-hyperbolic dependence between them, [I.sub.L] = [square root of ([P.sub.L])]/[square root of ([R.sub.L])]. The source-to-gate voltage [V.sub.SG7a] of the MOSFET [M.sub.7a] also increases rapidly, and the drain-to-source voltage [V.sub.DS1a] of the MOSFET [M.sub.1a] decreases rapidly.

Generated power [P.sub.L] of 5 mW of the proposed controllable constant power generator for variable load resistances 500 [ohm] < [R.sub.L] < 1.5 k[ohm] is shown in Figure 8. Relative error of generated power is -0.6% < [E.sub.L] < 0.1%. The generated power is calculated (6), and the system is calibrated for the load resistance of 1 k[ohm].

Generated powers [P.sub.L] = {0.5 mW, 1 mW} of the proposed controllable constant power generator for variable load resistances 1 k[ohm] < [R.sub.L] < 15 k[ohm] are shown in Figure 9. Generated powers PL = {2 mW, 3 mW, 4 mW, 5 mW, 6 mW, 7 mW, 8 mW, 9 mW} of the proposed controllable constant power generator for variable load resistances 400 [ohm] < [R.sub.L] < 5.5 k[ohm] are shown in Figure 10. Table 1 shows summarized results of the proposed controllable constant power generator. The range of resistive load [R.sub.L], for different values of dissipated power [P.sub.L], as well as the values of corresponding control voltages [V.sub.C1] and [V.sub.C2] is shown. The main demand was that the relative error of generated power is [absolute value of ([E.sub.L])] < 2%. For smaller generated power 0.5 mW [less than or equal to] [P.sub.L] [less than or equal to] 4 mW, the load resistance dynamic range is larger. It ranges from 15 (1 k[ohm] [less than or equal to] [R.sub.L] [less than or equal to] 15 k[ohm], for [P.sub.L] = 0.5 mW) to 7 (0.4 k[ohm] [less than or equal to] [R.sub.L] [less than or equal to] 2.8 k[ohm], for [P.sub.L] = 4 mW). For larger generated power 5 mW [less than or equal to] [P.sub.L] [less than or equal to] 9 mW, the load resistance dynamic range is smaller. It ranges from 5.5 (0.4 k[ohm] [less than or equal to] [R.sub.L] [less than or equal to] 2.2 k[ohm], for [P.sub.L] = 5 mW) to 2.4 (0.5 k[ohm] [less than or equal to] [R.sub.L] [less than or equal to] 1.2 k[ohm], for [P.sub.L] = 9 mW).

For smaller generated powers, the minimal value of the load resistance is limited by the input voltage offset of the CCII whose input is connected to the active terminal of the resistive load. That offset voltage is not constant over the all input voltage range of the current conveyor. Small absolute change of the offset voltage produces large enough relative change of the current [I.sub.3] that leads to the larger relative error of the generated power.

The main limitation for load resistance dynamic range, for all generated powers, is the supply voltage that directly affects the input voltage range of the CCII whose input is connected to the active terminal of the resistive load and the output current range of the multiplier/divider circuit. With larger supply voltage, it also would be possible to generate larger powers, as well as the larger range of generated powers.

In order to prove that the proposed controllable constant power generator is not particularly influenced by the process parameter variations, Monte Carlo simulations have been performed. The following process parameters have been changed within Monte Carlo simulations: carrier mobility, threshold voltage (for the source-to-bulk voltage VSB = 0), body effect coefficient, and channel length modulation coefficient of all MOSFETs, as well as the resistances [R.sub.1], [R.sub.2], and [R.sub.REF]. These values have been changed for 10% related to the nominal values for 100 runs. The nominal value of the generated power of PL = 5 mW is changed with process parameter variations from 4.5 mW to 5.6 mW for the load resistance 500 [ohm] < [R.sub.L] < 1.5 k[ohm]. By analyzing the individual influence of a certain process parameter variations, it can be shown that the change of the generated power is dominantly caused by the variations of the resistances [R.sub.1], [R.sub.2], and [R.sub.REF]. Although there is a change in the value of the generated power, it is important to stress that the relative error of the generated power is not affected by the process parameter variations. The absolute values of these relative errors range from 0.02% to 2.65% only. These relative errors are calculated related to the power generated for the load resistance [R.sub.L] = 1 k[ohm] for each corresponding run. Distribution of these relative errors in the form of a histogram is shown in Figure 11. The absolute value of the relative error is less than 0.5% in 28% runs, less than 1% in 73% runs, and less than 1.5% in 95% runs.

In order to investigate the temperature influence to the proposed design, the generated power [P.sub.L] = 5 mW of the controllable constant power generator for variable load resistance 0.5 k[ohm] < [R.sub.L] < 1.5 k[ohm] with the temperature used as a parameter Te{-20[degrees]C, -10[degrees]C, 0[degrees]C, 10[degrees]C, 20[degrees]C, 30[degrees]C, 40[degrees]C, 50[degrees]C, 60[degrees]C, 70[degrees]C, 80[degrees]C} has been simulated. Two types of the simulations have been performed. In the first one shown in Figure 12, the resistances [R.sub.1], [R.sub.2], and [R.sub.REF] are constant, that is, temperature independent. In the second type shown in Figure 13, the temperature influence to the resistances [R.sub.1], [R.sub.2], and [R.sub.REF] is modeled by using the linear temperature coefficient [alpha] = -3x[10.sup.-3]/K. This is the typical value of the linear temperature coefficient of the resistor made by using a high resistivity poly in a standard 0.35 f m CMOS technology. The relative error is calculated related to the power generated for the load resistance [R.sub.L] = 1 k[ohm] at T =27[degrees]C. For the temperature-independent resistance [R.sub.1], [R.sub.2], and [R.sub.REF] (Figure 12), the absolute value of the relative error is up to 8%. On the other hand, for the temperature-dependent resistances [R.sub.1], [R.sub.2], and [R.sub.REF] (Figure 13), the absolute value of the relative error ranges is up to 12%. It is clear that the proposed controllable constant power generator is dominantly influenced by the temperature variations of the resistances [R.sub.1], [R.sub.2], and [R.sub.REF] compared to the influence of the temperature variations of the active components. In order to reduce the temperature influence to the proposed design, according to the relation (6), either the resistors [R.sub.REF] and Rx, or [R.sub.REF] and [R.sub.2] have to be of the same type, while either the resistor [R.sub.2] or the resistor [R.sub.1] has to be designed with predetermined temperature coefficient (e.g., zero temperature coefficient). To that aim, either the resistor [R.sub.2] or the resistor [R.sub.1] can be designed as a composite one [13-15] with predetermined (zero) temperature coefficient. With this composite resistor, it can be expected that the overall temperature influence to the proposed controllable constant power generator will be similar to that shown in Figure 12 or even smaller. For the specific application of the proposed design in the plant tissue humidity measurements in the open arable field, the temperature range of interest is from 0[degrees]C to 50[degrees]C. In that case, the absolute value of the relative error is up to 3.5% for the temperature-independent resistances [R.sub.1], [R.sub.2], and [R.sub.REF] and up to 8% for the temperature-dependent resistances [R.sub.1], [R.sub.2], and rref.

Simulations of the frequency response of the CCII [M.sub.11]-[M.sub.23] (Figure 3) are shown in Figures 14 and 15. The DC biasing voltage at the terminal Y of the CCII is used as a parameter and is changed from 0.7 V to 3.28 V with a step of 0.43 V. This DC biasing voltage corresponds to the DC voltage [V.sub.L] across the resistive load [R.sub.L] for the generated powers 0.5 mW < [P.sub.L] < 9 mW and corresponding load resistance range. The load at the terminal Z is presented by the wide-swing current mirror [M.sub.24]-[M.sub.27], with the drain of the MOSFET [M.sub.27] connected to the supply voltage source [V.sub.DD]. The CCII has been optimized to achieve the gain-peaking less than 3 dB in the frequency responses for all ranges of the DC biasing voltage at the terminal Y of the CCII. The frequency voltage transfer characteristic [v.sub.x]/[v.sub.y] is shown in Figure 14. The bandwidth ranges from 39 MHz ([V.sub.Y] = 0.7V, [P.sub.L] = 0.5 mW) to 125 MHz ([V.sub.Y] = 3.28 V, [P.sub.L] = 9 mW). The frequency transconductance transfer characteristic [i.sub.z]/[v.sub.y] is shown in Figure 15. The bandwidth ranges from 39 MHz ([V.sub.Y] = 0.7 V, [P.sub.L] = 0.5 mW) to 137 MHz ([V.sub.Y] = 3.28 V, [P.sub.L] = 9 mW).

In order to prove that the proposed controllable constant power generator is stable, simulations of the transient response to a step change of the load resistance [R.sub.L] have been performed. The voltage-controlled resistor [12, 16] is used as the resistive load [R.sub.L] in order to simulate the step change of the resistance, Figure 16. The voltage follower within the voltage-controlled resistor is designed similar to that in [12], but with MOSFETs only. The resistors within the resistive voltage divider have the same resistances, R3 = R4. The load resistance is a step changed from [R.sub.L] = 0.707 k[ohm] to [R.sub.L] = 1.299 k[ohm], as the control voltage is a step changed from [V.sub.C] = 2.5 V to VC = 1.6 V. The rise time and the fall time of the load resistance are 28 ns and 19 ns, respectively. The voltage [V.sub.L] across the voltage-controlled resistor (resistive load [R.sub.L]) is shown in Figure 17. The product of the voltage [V.sub.L] and the current [I.sub.L] of the voltage-controlled resistor is constant and equal to [P.sub.L] = [V.sub.L][I.sub.L] = 5 mW. It can be seen that there is no overshoot in the transient responses which confirms the unconditional stability of the proposed design predicted by the mathematical model expressed by (7), (8), (9), (10), (11), and (12) and Figures 5 and 6. In addition, it can be estimated that the largest frequency bandwidth in the considered example is up to 5 MHz.

5. Discussion and Conclusions

Proposed controllable constant power generator based on multiplier/divider circuit is designed and simulated in 0.35 [micro]m CMOS technology. It is possible to generate small power from 0.5 mW to 1 mW for load resistance from 2.5 k[ohm] to 10 k[ohm] (variation from -50% to 100%, for the load resistance [R.sub.L] = 5 k[ohm]), with the relative error of generated power less than 1.2%. These results are shown in Table 2. Also, it is possible to generate larger power from 1 mW to 7.8 mW for load resistance from 0.5 k[ohm] to 1.5 k[ohm] (variation of [+ or -]50%, for the load resistance [R.sub.L] = 1 k[ohm]), with the relative error of generated power less than 2%. These results are shown in Table 3. The circuit is optimized for 5 V single supply. The ratio of the largest voltage drop across the resistive load and the supply voltage ([[V.sub.L].sub.max]/[V.sub.DD]) is 68%, which is a better result than 58% in [1], 40.6% in [3], and 44% in [4-6]. The supply voltage and power dissipation of the circuit are limiting factors in many applications, especially in the open field, powered by the solar cells. For different applications, where power consumption of the circuit is not critical, it would be possible to generate larger power, with wider load resistance dynamic range, with a higher value of the supply voltage.

Compared to the design presented in [1], proposed controllable constant power generator, for the load resistance range from 500 Q to 1.5 k[ohm], has the smaller range of generated power, with the same level of relative error, but with the 5 V single supply, compared to 7 V single supply. The design presented in [1] has larger load resistance dynamic range, but with 10 V single supply. Compared to the design presented in [3], proposed controllable constant power generator, for the load resistance range from 500 Q to 1.5 k[ohm], has the smaller range of generated power, but the smaller relative error with the 5 V single supply, compared to [+ or -]5 V supply voltage. The proposed controllable constant power generator also has larger load resistance dynamic range for the particular generated power, compared to the design presented in [3]. The largest relative error of the proposed design is 6 times smaller than in [10] for the same load resistance range, for the generated power 0.5 mW < [P.sub.L] < 12 mW. The frequency bandwidth of the proposed controllable constant power generator is approximately 500 times larger than in [1] and more than 6400 times larger than in [9]. The performance comparison between the proposed controllable constant power generator and controllable constant power generators presented in [1, 3], for resistive load 0.5 k[ohm] < [R.sub.L] < 1.5 k[ohm] is given in Table 4. The proposed design has no stability problems for all generated powers over a wide range of the resistive loads. Based on achieved results, it can be concluded that the controllable constant power generator can be used in various thermal-based sensor applications.

Conflicts of Interest

The author declares that there is no conflict of interest regarding the publication of this paper.

https://doi.org/10.1155/2018/3747325

Acknowledgments

This work has been supported by the Ministry of Science of Montenegro and the HERIC project through the BIO-ICT Centre of Excellence (Contract no. 01-1001).

References

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[16] N. Tadic and D. Gobovic, "A voltage-controlled resistor in CMOS technology using bisection of the voltage range," Proceedings of the 17th IEEE Instrumentation and Measurement Technology Conference [Cat. No. 00CH37066], vol. 50, 2001no. 6, 2001.

Milena Zogovic Erceg

Faculty of Electrical Engineering, University of Montenegro, Dzordza Vasingtona bb, 81000 Podgorica, Montenegro

Correspondence should be addressed to Milena Zogovic Erceg; milena.zogovic@gmail.com

Received 1 September 2017; Revised 26 November 2017; Accepted 6 December 2017; Published 4 March 2018

Academic Editor: Belen Calvo

Caption: Figure 1: The principle of operation of the proposed controllable constant power generator.

Caption: Figure 2: Multiplier/divider circuit schematic [8].

Caption: Figure 3: Complete circuit schematic of the proposed controllable constant power generator.

Caption: Figure 4: Small-signal model of the second generation current conveyor [11, 12].

Caption: Figure 5: The absolute value of the loop gain frequency characteristic of the proposed controllable constant power generator, for the lower limit of the resistive loads and for the appropriate generated powers.

Caption: Figure 6: The absolute value of the loop gain frequency characteristic of the proposed controllable constant power generator, for the upper limit of the resistive loads and for the appropriate generated powers.

Caption: Figure 7: Current [I.sub.L] flowing through the resistive load versus voltage [V.sub.L] across the resistive load of the proposed controllable constant power generator, for generated power [P.sub.L] = 5 mW. The current -I([R.sub.L]) is, in fact, the current IL. The voltage [V.sub.2]([R.sub.L]) is the voltage [V.sub.L].

Caption: Figure 8: Generated power PL versus load resistance [R.sub.L] of the proposed controllable constant power generator, for control voltages [V.sub.C1] = 1.5V and [V.sub.C2] = 2.67 V. The current -I([R.sub.L]) is, in fact, the current IL. The voltage [V.sub.2]([R.sub.L]) is the voltage [V.sub.L].

Caption: Figure 9: Generated powers PL = {0.5 mW, 1 mW} versus load resistance [R.sub.L] of the proposed controllable constant power generator. The current -I([R.sub.L]) is, in fact, the current IL. The voltage [V.sub.2]([R.sub.L]) is the voltage [V.sub.L].

Caption: Figure 10: Generated powers PL = {2 mW, 3 mW, 4 mW, 5 mW, 6 mW, 7 mW, 8 mW, 9 mW} versus load resistance [R.sub.L] of the proposed controllable constant power generator. The current -I([R.sub.L]) is, in fact, the current [I.sub.L]. The voltage [V.sub.2]([R.sub.L]) is the voltage [V.sub.L].

Caption: Figure 11: Distribution of the absolute value of the relative error ER.

Caption: Figure 12: The generated power [P.sub.L] = 5 mW of the proposed controllable constant power generator versus load resistance for temperatures T[member of]{-20[degrees]C, -10[degrees]C, 0[degrees]C, 10[degrees]C, 20[degrees]C, 30[degrees]C, 40[degrees]C, 50[degrees]C, 60[degrees]C, 70[degrees]C, 80[degrees]C}, with temperature-independent resistors. The current -I([R.sub.L]) is, in fact, the current [I.sub.L]. The voltage [V.sub.2]([R.sub.L]) is the voltage [V.sub.L].

Caption: Figure 13: The generated power [P.sub.L] = 5 mW of the proposed controllable constant power generator versus load resistance for temperatures T[member of]{-20[degrees]C, -10[degrees]C, 0[degrees]C, 10[degrees]C, 20[degrees]C, 30[degrees]C, 40[degrees]C, 50[degrees]C, 60[degrees]C, 70[degrees]C, 80[degrees]C}, with temperature-dependent resistors. The current -I([R.sub.L]) is, in fact, the current [I.sub.L]. The voltage [V.sub.2]([R.sub.L]) is the voltage [V.sub.L].

Caption: Figure 14: The frequency voltage transfer characteristic [v.sub.x]/[v.sub.y]. The voltage V([R.sub.REF]:2) is, in fact, the voltage [v.sub.x].

Caption: Figure 15: The frequency transconductance transfer characteristic [i.sub.z]/[v.sub.y]. The current ID([M.sub.26]) is, in fact, the current [i.sub.z].

Caption: Figure 16: The circuit used for simulations of the transient response to a step change of the load resistance [R.sub.L] using voltage-controlled resistor.

Caption: Figure 17: The output voltage of the controllable constant power generator for step change of the resistive load from [R.sub.L] = 0.707 k[ohm] to [R.sub.L] = 1.299 k[ohm]. The voltage V([M.sub.1vcr]:d) is, in fact, the output voltage of the controllable constant power generator in this analysis.

Table 1: Values of generated power PL, resistive load RL, control voltages [V.sub.C1] and [V.sub.C2], for relative error of generated power [absolute value of ([E.sub.R])] < 2%. [P.sub.L] [mW] [R.sub.L] [k[ohm]] [V.sub.C1] [V] [V.sub.C2] [V] 0.5 1 < [R.sub.L]< 15 0.67 0.6 1 1 < [R.sub.L]< 10 1.33 0.6 2 0.5 < [R.sub.L]< 5.5 0.6 2.67 3 0.4 < [R.sub.L]< 3.7 0.9 2.67 4 0.4 < [R.sub.L]< 2.8 1.2 2.67 5 0.4 < [R.sub.L]< 2.2 1.5 2.67 6 0.4 < [R.sub.L]< 1.8 1.8 2.67 7 0.4 < [R.sub.L]< 1.6 2.1 2.67 8 0.4 < [R.sub.L]< 1.4 2.4 2.67 9 0.5 < [R.sub.L]< 1.2 2.7 2.67 Table 2: Values of generated power [P.sub.L] and corresponding relative error [E.sub.R], for resistive load 2.5 k[ohm] < [R.sub.L] < 10 k[ohm]. [P.sub.L] (mW) [E.sub.R] (%) 0.5 -0.8 < [R.sub.L]< 1.2 1 -0.9 < [R.sub.L]< 0.5 Table 3: Values of generated power [P.sub.L] and corresponding relative error [E.sub.R], for resistive load 500 [ohm] < [R.sub.L] < 1.5 k[ohm]. [P.sub.L] (mW) [E.sub.R] (%) 2 -2 < [R.sub.L] < 1.5 3 -1.95 < [R.sub.L] < 0.6 4 -1.9 < [R.sub.L] < 0.35 5 -0.6 < [R.sub.L] < 0.1 6 -0.1 < [R.sub.L] < 0.3 7 -0.7 < [R.sub.L] < 0.2 7.8 -1<[R.sub.L] <2 Table 4: Performance comparison between the proposed controllable constant power generator and previous controllable constant power generators. [1] [3] [[absolute value of ([E.sub.R] (%))].sub.max] 2.2 3 [P.sub.Lmin] (mW) 0.48 -- [P.sub.Lmax] (mW) 10.8 11 [R.sub.Lmin] (k[ohm]) 0.5 0.5 [R.sub.Lmax] (k[ohm]) 1.5 1.5 Supply voltage (V) 7 [+ or -]5 [V.sub.Lmax]/[V.sub.DD] (%) 58 40.6 [f.sub.-3dB] (kHz) 10 -- This work * [[absolute value of ([E.sub.R] (%))].sub.max] 2 [P.sub.Lmin] (mW) 2 [P.sub.Lmax] (mW) 7.8 [R.sub.Lmin] (k[ohm]) 0.5 [R.sub.Lmax] (k[ohm]) 1.5 Supply voltage (V) 5 [V.sub.Lmax]/[V.sub.DD] (%) 68 [f.sub.-3dB] (kHz) 5000 * Simulated.

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Title Annotation: | Research Article |
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Author: | Erceg, Milena Zogovic |

Publication: | Journal of Sensors |

Date: | Jan 1, 2018 |

Words: | 7508 |

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