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45 GHz mm-wave phase-locked DRO.

45 GHz mm-Wave Phase-Locked DRO

Introduction

Users of current mm-wave phase-locked sources use fundamental sources at half or a quarter of the output frequency and multiply the fundamental frequency signals to the final output frequency. This approach has several disadvantages. They include the need for a frequency multiplier that is difficult to align and optimize for good performance; the need for high level drive power to the multiplier; the need for output filtering to suppress the input frequency signals; and the need for an additional amplifier at the output. A new design approach eliminates all of these disadvantages. The fundamental mm-wave phase-locked DRO is based upon a fundamental voltage tuned DRO at the output frequency locked to a reference signal via a proprietary sampling phase locked loop, as shown in Figure 1. The contribution to spurious signals and subharmonic content normally associated with the traditional multiplier approach is not present. Table 1 lists specifications of the mm-wave phase-locked DRO.

Design and Construction

DRO

The DRO uses a low noise GaAs FET that has 9.5 dB gain at 45 GHz. The oscillator design is based on a series feedback DRO, realized on thin-film alumina. Mechanical tuning of 500 MHz is achieved with a standard tuner mounted above the dielectric resonator. Electrical tuning is achieved by using either a varactor method or a DC bias change of the oscillator method, and is subject to specific requirements. DC bias change has the advantage of better phase noise. The oscillator power is boosted to the required output power through use of two amplifier stages using the same FET.

Sampling Loop

The sampling loop is a proprietary design technique and is used in PLOs up to 24 GHz. This technique eliminates the need for digital frequency dividers at microwave frequencies, has low power consumption and does not create additional noise. The sampling phase detector/comb generator, shown in Figure 2, uses discrete components on standard printed circuit board materials. By fabricating the MIC on thin-film alumina, the parasitic elements of the components are minimized and the harmonic generation of the step recovery diode (SRD) is increased to above 45 GHz. At this frequency range, the SRD can sample the free running DRO and achieve phase lock. The reference signal frequency may be 100 MHz to 1 GHz.

Figure 3 shows the phase noise plot of a 22.4 GHz unit. Figure 4 shows a simulation of a 38.3 GHz DRO, with an estimated phase noise of 100 dBc/Hz at 100 kHz frequency offset, locked to standard 100 MHz crystal oscillator.

Conclusion

The benefits of the described mm-wave phase-locked DRO design approach over current solutions include lower cost, small package size, lower power consumption and enhanced spectral purity.

COPYRIGHT 1991 Horizon House Publications, Inc.
No portion of this article can be reproduced without the express written permission from the copyright holder.
Copyright 1991 Gale, Cengage Learning. All rights reserved.

Article Details
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Title Annotation:dielectric resonator oscillator
Publication:Microwave Journal
Article Type:Cover Story
Date:Apr 1, 1991
Words:455
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