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3D IC stacks: myth or reality? Exploring the potential of 3D ICs.

Has the mythical unicorn been discovered? In a future utopian 3D IC world, heterogeneous digital, analog/mixed signal, RF, memory, and MEMS tiles will peacefully coexist. Each tile will be designed and fabricated in the most appropriate technology based on its intended function. Manufacturing and time-to-market will be enhanced by inherently smaller die.

New life will be breathed into older technology nodes, being used to fabricate dedicated MEMS and AMS/RF functions. New technology nodes will provide greater performance at lower power and lower cost, for pure digital designs. Repairable memory stacks, operating at higher frequencies, over shorter interconnect distances will enable unforeseen applications.

At the system level we will see higher performance, decreased power, overall smaller footprint, increased reliability, and cost reduction.

Products and application areas

The 3D IC market has been seeded with the Hybrid Memory Cube and high performance FPGA stacks, such as Xilinx's Virtex-7. Existing applications include high performance memory and sensor applications. Three-dimensional memories are faster, cheaper, and require less power. Removing logic from a memory chip allows room for advanced error detection, correction, and recovery, leading to repairable memory.

Sensors in a 3D stack can be placed closer together, with control logic on a different layer, providing highly increased resolution. Early adopters of this technology were able to provide advanced integration for a small price difference. The next wave will be infrastructure based networking, SAN, and supercomputing applications which can withstand a small premium and benefit from a more complete package and less complex PCB.

Killer apps will come from highly integrated solutions that cannot be comparably provided in 2D systems. A 3D stack allows integration of many disparate components to deliver a complete system in a package. Adoption for consumer products will occur as cost reductions, enabled by a proliferation of providers and maturation of the technology, allow 3D to become mainstream.

System-level design considerations

3D IC will bring increased packaging complexity and cost, however, there will be cost savings occur at the system level. There are many aspects to these savings: less board space, smaller number of PCB interconnects (with improved reliability), and lower cost die. In addition, system performance improves due to high speed interconnects over a shorter distance, leading to less power to be dissipated.

With this increased complexity, the savvy integrator has an extensive checklist of requirements, matched against wafer fab, assembly, and test house capability. Today the customer is the epicenter, and there is limited interaction between vendors. 3D stacking requires greater interaction between vendors, and limited interaction customer to vendor.

Some aspects to be considered: a) Die planarity is critical to allow die to die bonding; b) Proper die orientation for multiple chips; c) is die padding required to match street sizes with die from different foundries; e) testability/quality of the various die in the package; f) is thin wafer handling required; and g) a much more complex supply chain integrating more participants in the package integration process (i.e. extra die, interposer, etc.).

Additional equipment is needed at the final stages: aligner/bonder; TSV Plater; Bosch Etcher for sidewalls; pick & place tools; carriers for thin wafers; CMP at assembly; wafer grinder; edge grinder. These are not normal tools for an OSAT. Tool acquisition and training is required.


Testing becomes more complex and more critical. The integrator, whether an all-in-one fab, an OSAT, or a system integrator, must choose which steps in assembly require testing, how testing is performed, and where the most benefits occur. A potential large hidden cost exists if your test plan is not well conceived. Do you test after each die is added? Do you test only the final stack? Do you test in subsystems (CPU, Memory, Analog)?

With multiple assembly and test flows possible, each with pros/cons, optimizing flow will be challenging. The GSA 3D IC working group has a project underway to analyze these potential flows, and understand the benefits and drawbacks. (Find details about the project at


Several questions need to considered: Does 3D IC integration make ESD a bigger issue? What new, if any, ESD threats exist? How are ESD design practices impacted by 3D integration? Are existing ESD test methods applicable?

Are there new ESD threats?

Backside wafer thinning increases ESD buildup. Additional assembly/handling steps: die-to-die Bonding; package-to-package stacking; etc., generate additional ESD event possibilities. Process steps to expose TSV also produce potential ESD events. Wet grinding and dry polishing accumulate charge.

First TSV contact discharge is a concern, but die stacking assembly is likely to be better than or equal to current PCB pick & place assembly. Grounding corners, some edge, and center TSV allows the integrator to ensure first contact discharges CDM currents and lowers risk.

Therefore, assembly processes present no new ESD risks, as peak currents during assembly are lower than typical PCB assembly currents.

Are ESD design practices changed due to 3D IC?

Design practices will change, as most I/O are die-die; only I/O to the outside world will need full ESD protection. Designers have to consider stack Power Domain Crossings, as an SoC designer would.

CDM will get worse, as individual die pass wafer testing, but the stack fails. Failure could be related to stacking order--one arrangement works while others do not. CDM currents will find a path between every die in the stack and outside pins. Lastly, CDM currents will increase due to additional package size, increased circuits, and a larger number of interconnects.

Are current ESD models and test standards still applicable?

The 3D IC stack integrator may be acquiring die from different sources, without full design databases; each die design may be independently owned. This adds complications to failure debug. Failures can also be architecture dependent and vary based on stacking arrangements, independent of die used.

A complicating factor is that current ESD standards do not account for bare die, and in some cases cannot be tested against bare die, especially die with thousands of TSV's. Not only it will be difficult to find the root cause, but vendors and suppliers currently have no clear means of communicating ESD robustness for individual dies, leaving a lot of ESD robustness for the final design in the hands of the system architect.

After packaging, TSV connections cannot be directly tested for HBM/MM/CDM, thus failure debug becomes more difficult. Any failures will require full ATE flow and the ability to intelligently isolate failures. A curve tracer cannot be used to test HBM/MM in 3D a stack, eliminating a critical tool in debug. CDM can't be tested at wafer level (without specialized equipment); therefore testing occurs after packaging is completed. Lastly, emissions' testing becomes more difficult: how to determine where the emission signature is located.

ESD conclusion

In conclusion, no new ESD stresses are added. ESD design is more flexible, as not all I/O need full protection. HBM current paths are easier to architect, involving only external I/O to external I/O pins. CDM paths are more difficult to understand, as they are package dependent. A 3D stack will have higher CDM currents than an individual die would see in isolation, as CDM current will flow between every die in stack. Coordinating ESD designs amongst all parties with a die in the stack will be similar to system level design for Charged Board Model. The biggest challenge to be faced will be finding the root cause for any ESD/latchup/EOS failures from the field. This is especially true for multi-chip stacks with different and varying process technologies.

Many companies have 3D IC development underway, covering every aspect of the required ecosystem. This exciting technology paves the way for yet to be conceived high performance applications. Many organizations are defining standards to help ensure interoperability, while numerous conferences are devoted to this technology.

The Global Semiconductor Alliance continues to play a critical role in educating newcomers, providing insight into development efforts, and providing a neutral forum for the industry to gather and conquer mutual issues. Information in this article was extracted from Tezzaron and Certus Semi presentations to the GSA 3D IC working group, April 17, 2013. Details can be found at Other members of the 3D IC working group also contributed.

By Harrison Beasley, Technical Working Groups Manager, Global Semiconductor Alliance (GSA)
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Title Annotation:Integrated Circuits
Author:Beasley, Harrison
Publication:ECN-Electronic Component News
Date:Jul 1, 2013
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