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2 to 8 GHz high gain monolithic feedback amplifier.

2 to 8 GHz High Gain Monolithic Feedback Amplifier

Introduction

A state-of-the-art high gain, feedback GaAs monolithic amplifier chip has recently been developed. The SA-0167 amplifier chip covers the frequency range from 2 to 8 GHz. This amplifier chip provides a nominal gain of 12 dB with an output power level flatness of [+ or -] 0.5 dB, and an input/output impedance mismatch of 2:1 maximum across the frequency band.

The SA-0167 amplifier chip is a two stage design utilizing a small gate periphery FET (0.5 x 300 micron) for optimum small signal gain performance, moderate output power, and low current consumption. To decrease current consumption further, a series biasing arrangement is employed. A shunt resistive feedback technique is used in order to provide optimum broadband amplifier performance. The chip size is 0.12" x 0.08."

This MMIC amplifier circuit is configured to operate from a single polarity (positive) bias power supply. Flexibility exists in choosing the bias point (if the present values are not desired) of each of the two FETs. This can be accomplished through the use of off-chip source bias resistors.

A number of amplifier modules have been constructed using three of these two stage monolithic amplifier chips. The gain and flatness of these modules is 34 [+ or -] 1 dB, while the input and output impedance mismatch is less than 2:1 over the design band. The drain-to-source current consumption is less than 115 mA at 10 V. No hybrid circuitry (compensation networks or transmission line stubs) are required to optimize the amplifier response. The size of the final amplifier module measured 1.2 x 0.66 x 0.22 inches (excluding connectors).

Chip Design Description

The circuit consists of two self biased amplifier stages cascaded on a single chip. Several circuit topologies exist for designing MMIC amplifiers. Some of the prevalent approaches are feedback, reactive match, lossy match, and distributed amplifiers. The feedback approach was chosen in order to obtain good RF performance over the two octave frequency band while occupying a minimum chip area. Both the straight reactive and lossy match designs would not cover the 2-octave frequency band and achieve comparable performance. A distributed approach, though capable of meeting the desired RF performance, has low DC efficiency. The feedback configuration however, results in a slight degradation of the noise figure and available gain.

The SA-0167 circuit configuration consists of an input matching network, two MESFET feedback cells, an interstage matching network, and an output matching network as depicted in Figure 1. A photograph of the circuit is shown in Figure 2.

The negative feedback network is a shunt resistive structure. The network is connected between the gate (input) and drain (output) of the FET and feeds back part of the output signal to the input. This arrangement has the effect of trading off some of the available gain of the FET for a much improved input impedance match. Figure 3 shows a plot of the [S.sup.11] of the FET along with the FET and feedback arrangement. Note how the feedback circuit has clustered the frequency band of interest and caused the response to move closer to the center of the Smith chart, thus making it easier to match into the FET. A two stage feedback design offers the added advantage of being able to set the feedback resistance on the first stage to a low value (and trading off some of the available gain) in order to obtain a low input impedance match. Simultaneously, the feedback resistance of the second stage can be set to a higher value of yield increased gain.

Both the input and output matching circuits were synthesized using Super Compact * software. The resultant impedance matching structures consisted of four element "T" networks which are formed by two series inductors, a single shunt inductor, and a series capacitor which also serves as a DC block. To further improve the impedance match, small open circuited stubs were added to the input and output matching structures. The initial design efforts centered on a single feedback amplifier circuit. After achieving acceptable performance for a single stage, "two" of these stages were cascaded (forming the two stage amplifier chip) and the circuit elements were readjusted for optimum performance.

The "monolithic" components used in the design consist of two 0.5 x 300 [micrometer] four finger FETs, silicon nitride MIM (metal-insulated-metal) capacitors ranging in value from 0.2 to 18.5 pF, rectangular inductors (up to 5 nH), microstrip transmission lines, implanted resistors, and via-hole ground points for reduced inductive parasitic elements (over bond wire ground connections) and improved reliability.

The chip incorporates a DC self-bias mode. While the chip is required to operate in a self-bias mode, either a series or parallel bias configuratio of the two stages can be implemented through a single process change. When the parallel bias mode is used, the power supply voltage is +5 V and the total current is the sum of the current drawn by each of the two FETs. The bias point of each FET is set through the use of external resistors connected to the sources of the FETs. The flexibility of this arrangement allows the amplifier to be biased for maximum gain, power, noise figure, or selected temperature compensation methods. The series bias configuration differs from the parallel bias mode in that the two stages are connected in series, the power supply voltage is +10 V, and the current required is equal to that of a single stage. Note that the bias points for the FETs must be identical in this configuration.

FET Processing

The amplifiers were fabricated using a standard MMIC process. This process utilizes an N+/N implant structure formed by direct ion implantation into undoped GaAs. The N+/N implant is used for the FET active layer and for bulk resistors. The 0.5 micron gates are formed optically through the use of a tri-level resist structure. The gates are self-aligned to the N+ layer by recess etching prior to the metalization and liftoff. Self-aligning provides a high degree of reproducibility in the placement of the gate electrode with respect to the N+ layer. This contributes to the stability of the device performance.

Experimental Results

Full DC and S-parameter characterization of the MMIC devices is accomplished using a Cascade probe wafer test stand which incorporates an auto-prober for automatic circuit evaluation. The performance plots in Figures 4 and 5 represent typical device data. Figure 4 illustrates the gain performance of the chip (the nominal gain is 12 [+ or -] 0.5 dB). Figure 5 shows the input and output matches for the chip (in both cases better than 1.8:1). The measured output power at the 1 dB compression point is +13 dBm minimum, while the noise figure is 7.5 dB maximum. These are room temperature measurements taken with the series biased version of the MMIC amplifier. Figure 6 shows the gain vs. temperature response results of the amplifier in the series bias configuration.

Yield Considerations

The production yield for a 2" diameter wafer with 228 possible circuit sites has averaged about 37 percent using DC and RF testing. Contributing to this high value is the repeatable self-aligned fabrication process utilized here. Figure 7 illustrates the repeatability and uniformity of gain performance of all the functioning chips on a 2" wafer. The number of RF functional chips across the wafer was 63. The variation in nominal gain across the wafer is only [+ or -] 1.5 dB.

Amplifier Modules

The amplifier modules used a nickel-plated Kovar housing body measuring 1.2" x 0.66" x 0.22". It has three Copper-Tungsten (for thermal expansion considerations) carrier assemblies integrated into each of the modules. Each carrier assembly consists of a single 2 to 8 GHz amplifier chip and input and output launching substrates. Figure 8 shows a typical amplifier assembly. The voltage supply for the module is +10 V and the current consumption is 115 mA. The gain of the amplifier module is 34 [+ or -] 1 dB and the input and output impedance mismatches are 1.8:1 maximum over the design band. The gain and return loss is plotted in Figure 9. The measured single sideband noise figure is 7.8 dB (worst case) at 2 GHz and 6.5 dB at 8 GHz. The output power at the 1 dB compression point is 13.5 dBm minimum and the saturated output power is 16.4 dBm minimum.

A comparison of the reliability between the monolithic module approach vs. an equivalent hybrid amplifier module shows a factor of 2x improvement. This is primarily because of the number of wire bonds in the two circuit approaches (both of which meet the same form, fit and function). The following expression, out of MIL-HDBK-217E, was used to calculate the reliability of a 2 to 8 GHz monolithic amplifier carrier assembly (using the SA-0167 device) and an equivalent 2 to 8 GHz hybrid amplifier assembly.

[[lambda].sub.p] = { [[Sigma]N.sub.c][[lambda].sub.c][[pi].sub.g] +

[[Sigma]N[sub.i][[lambda].sub.i] + [[lambda].sub.s]] [[pi].sub.f][[pi].sub.e]} [[pi].sub.q][[pi].sub .d]

where,

[N.sub.c] = Number of FETs (2 for monolithic and 2 for hybrid) [[lambda].sub.c] = FET failure rate (0.2 for both monolithic and hybrid)

(based on an MTBF = 5 x 10[sup.6] Hrs/Failure at [T.sub.i] = 150 [degrees] C [[pi].sub.g] = Constant for Integrated Circuit (1) [N.sub.i] = Number of bond wires interconnections (12 for monolithic and 26 for the hybrid) [[lambda].sub.i] = Bond wire failure rate @+85 [degrees] C (0.0017) [[lambda].sub.s] = Failure rate associated with package (neglected) [[lambda].sub.f,e,q,d] = Circuit function, environment, quality, and density factors 1.25, 4, 1, 1 (mono.)/ 2 (hybrid) respectively).

Applications

The SA-0167 MMIC amplifier was developed principally for use in high gain amplifier modules where low current operation is important. The series biasing configuration will conserve half the current (40 mA) of the parallel biasing arrangement by utilizing higher voltages (typically +12 V) provided in most subsystem or system applications. Temperature compensation of an amplifier can readily be accomplished by biasing the SA-0167 device in the parallel bias mode. This will enable the gain of the FETs to be controlled through changes in the source resistance (off-chip in this configuration) over temperature. Changes in the source resistance can be accomplished with the use of a thermistor circuit arrangement. Besides temperature compensation, this mode allows for a choice of bias points for the two FETs. The first stage of the chip can be biased for lower gain and better noise figure, while the bias voltage applied to the second stage can be increased for additional gain.

The chip can also be used in VCO applications. One of the needs for a typical VCO is to have a buffer amplifier following the oscillator to provide gain, moderate output power, and high isolation. The amplifier chip can accomplish this by following up the oscillator. The isolation across the frequency band is greater than 30 dB. The output power is moderate for this device type and if more power is required, the chip could be followed by a higher power stage.

Conclusion

A monolithic amplifier gain stage was developed covering the 2 to 8 GHz frequency band with a nominal gain of 12 [+ or -] 0.5 dB, an input/output impedance mismatch of less than 2:1, and moderate output power. It has a flexible DC biasing arrangement. The circuit shows a high degree of insensitivity to processing variations, resulting in high uniform yield.

Acknowledgment

The work described in this paper was carried out using Sanders IR&D funding. The author expresses thanks to Joe Lombardi for his support in the testing of the chip and Dana Hapgood for his many helpful suggestions in the preparation of this paper.

Martin A. Priolo is a microwave engineer at Sanders Associates Inc. with five years of experience in the field of defense microwave electronics design. He is currently working at the Sanders Microelectronics Center and is involved in the design, develoment and evaluation of MMIC circuitry and integrated modules in the 0.5 to 18 GHz frequency range. Previous work included hybrid and monolithic amplifier module development, IMPATT diode oscillator design in C- and X-band, work with expendable decoys and development of passive and active quasi-optical components in the 75 to 110 GHz frequency band. Priolo received his BSEE from Pennsylvania State University in 1983 and an MSEE in microwave engineering from the University of Massachusetts in 1985. He has taught in-house microwave courses and is a member of the IEEE.

Curtis Barratt is the manger of pilot production for GaAs MMICs at Sanders Microelectronics Center. He has been involved in the development of the pilot production process at Sanders for the past five years. Prior to Sanders, Barratt worked at M/A-Com Semi-conductor Products on discreet GaAs microwave devices including Gunn and Varactor diodes as well as FETs. Mr. Barratt received his Bachelor's in chemistry from the University of Massachusetts at Amherst in 1979.

Gary St. Onge has been a member of the technical staff at Sanders' Microwave Technology Center for the past three years. He has been involved in the design and test of various broadband MMIC circuits including digitally controlled phase shifters adn attenuators. St. Onge received his BSEE from the University of Massachusetts at Amherst in 1985. He is presently pursuing an MSEE at Northeastern University. He is a member of IEEE, Tau Beta Pi, and Eta Kappa Nu engineering societies.
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Title Annotation:technical feature
Author:Priolo, Martin; Barratt, Curtis; St. Onge, Gary
Publication:Microwave Journal
Date:Aug 1, 1989
Words:2271
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