16 and 32 W linear power GaAs FETs challenge silicon bipolar transistors in L-band.
Silicon bipolar transistors are used for power amplification at frequencies through 2 and 3 GHz because silicon material is less expensive than GaAs and the devices are fabricated with a well-established process technology, while providing gain on the order of 6 dB per stage at L-band frequencies.
However, GaAs FETs do offer one important advantage over bipolar transistors as L-band power amplifiers; they offer power gains on the order of 14 dB. This is twice the gain per device so the number of stages required in a power amplifier can be reduced substantially. Also, the FET die can be mounted directly on a gold-plated metal carrier.
The main disadvantage of power GaAs FETs is that they operate at a low bias level, 9 V compared to 20 to 25 V for power bipolar transistors. For high power devices such as these, [I.sup.2.R] losses in the bias circuitry can be significant, in which case a lower operating voltage is a disadvantage.
There are many similarities in performance between the GaAs and silicon power devices. The power-added efficiency of power GaAs FETs is comparable to that of power bipolar transistors. Newer, higher breakdown voltage GaAs FETs can be operated in class AB, increasing the power-added efficiency of GaAs FET amplifiers. Bipolar transistors may also be operated in class AB with similar results. Under linear operation, from small signal operation through power levels approaching 1 dB gain compression, distortion levels of GaAs FETs are not significantly different from those of bipolar transistors.
This article discusses narrowband multichip power FETs for operation in L-band frequencies, and how the transistors function in a linear power amplifier operating at 1.6 GHz.
Power GaAs FET Die
For this project, a standard 10 mm gate periphery FET die was used with a total of 80 gate fingers, each 125 [micrometer] wide and 0.5 [micrometer] long, with a gate to gate pitch of 20.5 [micrometer]. The structure was made up of 8 cells, with each cell consisting of a group of 10 fingers. The channel spacing was 6.5 [micrometer] and the channel recess 3.5 [micrometer]. The die measured 0.46 x 1.9 x 0.07 mm. This device is capable of operating at frequencies exceeding 10 GHz, with a nominal saturated output power of 4 W.
When a power amplifier is driven with several discrete carrier frequencies, such as a driver or output stage in a frequency-multiplexed communication system, the total peak power could drive the power transistor into saturation, even if the individual signals are at moderate power levels. It is important to characterize the communications power device under both small and large signal conditions. One approach to such characterization is to use the two signal method . Using this technique all four S-parameters may be measured. This leads to the simplified equivalent circuit shown in Figure 1.
The Building Block Carriers
Each building block carrier (BBC) is a partially-matched assembly comprising two FET dies mounted on a carrier, as shown in Figure 2.
The present application uses the FET in a 40 MHz bandwidth centered around 1.6 GHz. The circuit responds significantly differently at 1.6 GHz than at 10 GHz. At 1.6 GHz the gate capacitance makes the device input into a high-Q circuit, and plays a dominant role in determining the circuit's frequency response. At the output side, the drain capacitive reactance is very high, and may be neglected in relation to the effective FET output resistance. The FET offers high gain at 1.6 GHz. Typical gain of a single BBC is 15 dB at 1 dB gain compression.
The gate wires shown in Figure 2 are each 2.54 mm long, a length that is needed to resonate with the input gate capacitance at 1.6 GHz. The rest of the input circuit match is realized on a soft substrate, 0.030 in. thick RT/duroid 5880. (*1) On the drain side, a 0.003". thick barium tetratitanate substrate ([[epsilon].sub.r = 38]), together with bond wires, raises the impedance level to 9 ohms, with the remainder of the output circuit match realized on a soft substrate. Each BBC is built with leads to facilitate independent evaluation before its incorporation into a FET package. The BBC measures 3.81 x 10.16 mm.
16 and 32 W Power Transistors
To build a 32 W multichip transistor, four BBCs are mounted using solder preforms on a FET push-pull package, as shown in Figure 3. A push-pull configuration is chosen because of the numerous advantages it has over a single-ended circuit. 
With four FET dice mounted on each arm (Figure 3) of the push-pull circuit, the design problem is reduced to effectively combining the power output of four FET dice in parallel. This resulting hybrid transistor, with 80 mm of total gate periphery, is biased at 9 V and 8 amps for class A operation, and is capable of delivering 32 W of linear power with about 14 dB of associated gain, at 1 dB gain compression. This unit measures 10.41 x 41.35 mm.
The 16 W hybrid transistor (Figure 4) is biased at 9 V, 4 amps for class A operation, and is capable of delivering 16 W of linear power with more than 14 dB of gain, 1 dB GCP. The overall dimensions of the transistor package are the same as the 32 W transistor.
It is important to recognize the advantages of this building block approach over assembly of all constituent parts on a single carrier. The advantages include the carriers can be tested separately for qualification of the wafer; since only two dice are mounted on each carrier, the time duration at elevated temperatures during die attach is short, thereby avoiding possible damage; BBCs, once built, can be used to build 8 W, 16 W or 32 W devices as desired; and rework on a transistor, if required, is greatly simplified since only the defective BBCs need be removed and replaced.
Performance at 1.6 GHz
Three test amplifier fixtures have been designed and built to test 8 W BBCs, the 16 W and the 32 W transistors. The TF for BBCs is single-ended, not shown here, while the fixtures for 16 W and 32 W transistors are both of the push-pull type (Figures 6 & 7). The performance curves are chosen to illustrate the typical spread observed among devices built from several wafers. More than 150 BBCs, 20 16 W and 30 32 W transistors have been built to date.
The following tests have all been carried out at [V.sub.DS] = 9 V. The quiescent bias currents were 2 amps for a single BBC, 4 amps for the 16 W and 8 amps for the 32 W modules.
As expected, the BBC power output was typically 8 W at 1 dB compression with an associated gain of 15 dB as shown in Figure 5. The 16 W push-pull modules did indeed deliver 16 W at 1 dB compression with a gain of approximately 14.5 dB, as shown in Figure 6. The 32 W push-pull modules also worked well, although tuning was noticeably more difficult on the fixture than for the other devices. Figure 7 shows the fixture and the performance obtained. The fixture employs 25 ohm coaxial baluns on its input and output sides. Besides converting RF from unbalanced to balanced to drive the push-pull transistor, these baluns also provide impedance transformation from 50 to 12.5 ohms.
Intermodulation Test Results
The linearity of these modules has been measured using a two-tone intermodulation setup. The tone levels are held equal but varied over a wide range of power levels. The tone levels referred to in this article are the values monitored at the output of the fixture, as only these are relevant in a communication system. Also, the distortion products are referenced (in dBc) to the level of each tone. For brevity, [IMD.sub.3] results are reported only for the 32 W transistors.
Figure 8 shows the third-order intermodulation levels as a function of power output of each tone on several devices. It can be seen that for tone levels below 9 W (each tone), [IMD.sub.3] is better than -20 dBc, a very respectable figure for a 32 W amplifier.
Power FETs vs. Bipolar Transistors
For a given subsystem's electrical performance there are two approaches, one using power FETs and the other using conventional power bipolar transistors. Assume that our objective is to realize a linear amplifier with the following specifications:
* power output at 1 dB gain compression = 30 W or +44.8 dBm (min.)
* gain (1 dB compressed) = 25 dB (min.)
* [IMD.sub.3.,] two equal tones, each [is less than or equal to] 9 W at output, = -20 dBc (max.).
Five stages of amplification using commercially available silicon bipolar power transistors are needed, while only two stages are needed if we choose to use power FETs described in this article. The high gain of the FETs would mean that the driver amplifier need not put out a great deal of power, only 1.2 W are needed to drive each 32 W device. A single 16 W device easily can drive two 32 W devices in a balanced configuration without degradation of the system linearity, as it would still be operating at about 3 dB backed-off condition.
In the case of bipolar power transistors, the significantly lower perdevice gain would translate into a need for monstrous drivers. For example, to drive two 32 W linear amplifier modules employing silicon devices in a balanced configuration, a driver capable of delivering 16 W of linear power, or 32 W if we wish to maintain linearity through 3 dB backed-off operation, is needed.
It is clear that power FETs offer higher linear power output than today's linear bipolar counterparts. Power FETs also provide much higher gain, which translates into a smaller amplifier size, greater efficiency and considerable simplification of a subsystem design. FET linearity is comparable to that of bipolar devices, with equivalent power-added efficiency. Considering its performance as a whole, it is clear that the FET represents a cost effective alternative to bipolar transistors in L-band communications applications.
 S.R. Mazumder and P.D. van der Puije, "Two-Signal Method of Measuring the Large Signal S-Parameters of Transistors," IEEE Trans. MTT, Vol. 26, No. 6, pp. 417-420.
 R. Basset, "Three Balun Designs for Push-Pull Amplifiers," Microwaves, July 1980, pp. 47-52.
Chandra Khandavalli is currently a member of the technical staff and group leader in the Semi-conductor Division, Avantek Inc. Since joining Avantek in 1986, Khandavalli has been involved with the development of high power silicon-based transistors for cellular radio and INMARSAT applications, and of high power, high efficiency GaAs FET transistors and modules at frequencies ranging from 1.6 through 18 GHz. Prior to joining Avantek, Khandavalli was employed by TRW Semiconductors in Bordeaux, France, where he was engaged in the development of high power silicon bipolar transistors, and transmitting amplifier subsystems. Khandavalli received the Bachelor degrees in Science (BSc) in 1969 from Osmania University (India), and in Engineering (BE) in 1973 from the Indian Institute of Science. He was awarded the M. Tech. degree from Indian Institute of Science. He was awarded the M. Tech. degree from Indian Institute of Technology in 1975. He was employed by Tata Institute of Fundamental Research, where he worked until 1980 on the design of microwave components for radar subsystems using both waveguide and MIC techniques. In 1983 he obtained his Docteur Ingenieur degree from Universities de Limoges in France.
Jean-Raymond Basset is currently R&D circuit engineering manager, Power Joint Venture Group, Avantek Inc. His responsibilities include the circuit design of all FET power devices that require the development of new technology. Mr. Basset has 20 years of experience in microwave circuits and active devices, and has been with Avantek since 1984. Mr. Basset holds the License Es Sciences from Bordeaux University, France, and the Diplome D'Ingenieur Electronique et de Radioelectricite from ENSERB engineering school, France. He holds patents for Gunn oscillator and for push-pull circuits.
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|Title Annotation:||technical feature|
|Author:||Khandavalli, Chandra; Basset, Jean-Raymond|
|Date:||Sep 1, 1989|
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