Printer Friendly

100 Gb/s physical-layer testing tips and tricks.

Driven by on-demand video, cloud applications, social sharing, and much more, today's always-connected world has an insatiable craving for more bandwidth. With 10 Gb/s and 40 Gb/s falling to the wayside, the focus now is on deploying 100G, typically composed of four 25 Gb/s electrical channels feeding 100G optical transport systems.

While the rush to deploy 100G technology is in full swing, the industry still is trying to perform more efficient testing at 25+ Gb/s rates. This means designers need to understand how analog waveforms relate to digital signal bit error rates (BER). Consider this: a bit period at 25 Gb/s is just 40 ps. The jitter budget has all but disappeared. Less than 3 ps of random jitter (RJ) close the eye altogether, and emerging standards typically permit less than 700 fs of RJ. This places emphasis on the intrinsic jitter and noise of the measurement instruments used to evaluate the signaling.

Emerging 100 Gb/s and Related Standards

As is often typical, market demand is ahead of standards. Since most of the test specifications have not been published, the details summarized in Table 1 are typical of what to expect. However, for compliance testing, be sure to check the actual standards for specific numbers as they become available.

           Standard       Geometry          Reach     Data Rate

100 GbE  100GBA5E-LR4   4 SM Fibers    10 kM 40 kM   4x25.78125
                                                           Gb/s

         100GBASE-ER4

         100GBASE SR4   4 MM Fibers  [less than or   4x25.78125
         *                            equal to] 10         Gb/s
                                                 m

         100GBASE-CR4   4 Cables,                *            *
         *              Backplane

OIF-CEI  100GBASE-KR4
         *

         OIF 28G-SR     N Traces on     30 cm 15 *  19.90-28.05
                        PCB                     cm         Gb/s

         OIF-28G-VSR *

Fibre    32GFC          N Channels           TBA *      28.05 *
Channel                 Optical and                        Gb/s
                        Electrical

              BER

100 GbE  [less than or
             equal to]
           [10.sup.12]

         [less than or
             equal to]
           [10.sup.12]

         [less than or
             equal to]
           [10.sup.12]

OIF-CEI

         [less than or
             equal to]
           [10.sup.15]

Fibre    [less than or
Channel      equal to]
            [10.sup.12

Table 1. Summary of Emerging Standards

Standards marked with an asterisk have not
been released: consider the values speculative.


The two most established 100-GbE optical transmission specifications, both covered in IEEE 802.3ba, are long-reach 100GBASE-LR4 and extended-reach 100GBASE-ER4. The differences between them arc primarily at the receive end. The ER4 receiver has greater sensitivity and must pass a more difficult stress tolerance test than the LR4 receiver.

The short-reach 100GBASE-SR4 4x25 Gb/s low-cost, multimode (MM) standard along with those for electrical transport over cables and backplanes, 100GBASE-CR4, and 100GBASEKR4 are works in progress. When finished, the 100GBASE specifications will provide a complete suite of optical interconnect systems.

Implementation agreements (IAs) from the OIF-CEI do not prescribe compliance tests the way that IEEE 802.3ba 100 GbE or Fiber Channel specifications do. Instead, the emphasis is on informative and normative tests that attempt to assure component interoperability across standards. Normative tests are like compliance tests in the sense that the committee prescribes them to assure interoperability; informative tests are recommended to develop a more thorough understanding of performance and margin.

The short-reach IA OIF-28G-SR consists of multiple lanes at 19.90 to 28.05 Gb/s of differential pairs over 300 mm of PCB with up to one connection operating at BER < 10-15. The very short reach IA OIF-28G-VSR has not been published, but a preliminary version is available. It consists of multiple electrical lanes at 19.60 to 28.05 Gb/s for signaling between Serdes (called hosts in the IA) and transceivers (modules in the IA). The Serdes and transceiver can be separated by about 100 mm of PCB to a connector plus an additional 50 mm or so of conducting trace. The system is required to operate at BER < [10.sup.-15].

The high-rate Fibre Channel standard, 32GFC, has a data rate of 28.05 Gb/s. The confusing name scheme comes from the desire for the name of each generation to demonstrate that the payload rate, as opposed to the data rate, is double that of the previous generation. The confusion began with a large decrease in overhead in the transition from 8GFC to 16GFC when the data rate advanced from 8.5 to 14.025 Gb/s but the payload rate doubled from 6.4 to 12.8 Gb/s. The payload rate for 32GFC is 25.6 Gb/s, twice that of 16GFC, but the data rate, 28.05 Gb/s, is well short of that implied by the 32GFC abbreviation. Currently, the 32GFC has not been published, and the preliminary version has few reference values.

Testing 100G Systems

In a typical 100G systems, a Serdes serializes a signal and transmits four 25+ Gb/s differential pairs. The 25+ Gb/s electrical signals are transmitted from the Serdes to an optical transceiver. The transceiver retimes the signals and transmits optical versions on either single-mode (SM) or MM optic fibers. A second transceiver receives the optical signals, converts them to electrical, and transmits them to another Serdes for deserializing. The purely electrical version follows the same scheme without the intermediate transceiver-driven optical signaling.

Whether for transmitter or receiver testing, optical or electrical, patterns are required to test every aspect of a component or system. The pseudo-random binary sequences (PRBSn) are standardized patterns with every permutation of n bits. The OIF CID jitter tolerance pattern is designed to have the most aggressive elements of the PRBS31 plus 72-bit sequences of consecutive identical (CID) bits but at a manageable length.

Testing Optical Transmitters

Eye mask tests can be performed on either a low-noise equivalent time sampling oscilloscope or a bit error rate tester (BERT). In both cases, wide bandwidth optical-to-electrical receivers and clock recovery units are necessary. The clock recovery -3 dB bandwidth differs among specifications, typically BW =[f.sub.data]/1667. The optical-to-electrical receiver should apply a fourth-order Bessel-Thompson filter with a reference frequency of three-fourths the data rate, [f.sub.ref] = 3/4 [f.sub.data]. The filler is required to ensure that different test platforms can operate under uniform measurement conditions.

The random nature of a mask test is addressed by requiring a minimum hit ratio. The hit ratio is defined as the ratio of the number of mask violations to the total number of samples acquired per unit interval. Since this is a statistical measurement, the more hits, the greater the accuracy. A transmitter is compliant if it achieves a hit ratio less than 5x10-5.

Alternatively, it's both more statistically reliable and easier to measure the BER contour with an instrument like a sampling oscilloscope or BERT that deploys jitter and noise analysis software. As long as the BER = [10.sub.-6] contour is outside the mask, the transmitter passes the 5x[10.sup.-5] hit ratio eye test. The BER contour technique also makes it easier to see the passing margin.

Testing Optical Receivers

The optical receiver stress tests for the long-and extended-reach 4x25 Gb/s topologies (100GB ASE-LR4 and 100GB ASE-ER4) are similar except that greater sensitivity and robustness are required of ER4, as indicated in Table 2. At these data rates, a key challenge is producing compliant stress levels. With the appropriate options, a BERT can be used to generate a conformant, stressed eye using its internal impairment system for driving a tunable laser-based signal into the optical receiver device under test.

                    100GBASE-LR4     100GBASE-ER4  Frequency

Average Received  4.5 to-10.6 dBm  4.5 to -20.9
Power                              dBm

Sinusoidal        0.05 UI above
Jitter            Roll-Off
                  Frequency

Sinusoidal        Sum to J2 and                  0.1 to 2
Interference      J9                             GHz

RJ

J2 Jitter         0.3 UI

J9 Jitter         0.47 UI

Table 2. Summary of 100-GbE Stressed Receiver
Sensitivity Test Conditions

The sum of effects from all stressors is prescribed
to meet the vertical eye closure and J2 and J9 jitter
specifications.


Typically, this involves configuring the BERT to drive a Mach-Zehnder (MZ) optical modulator (OMA). Then tune the MZ bias to optimize I/0 symmetry. Next, sinusoidal jitter (SJ) is applied to the pattern generator clock to assure that the receiver can track low-frequency jitter.

Following this, Inter-Symbol Interference (ISI) is generated with a 4th order Bessel-Thompson filter. As specified by the IEEE 802.3ba stress-conditioning block, this 19-GHz low-pass filter characteristic removes higher order harmonics from the test generator output to permit a more consistent approach to measuring the vertical eye closure penalty and data dependent jitter (DDJ).

RJ is applied using a precision Gaussian noise generator. Gaussian RJ can be imposed on a signal by adding the noise and then subjecting the signal to a limiting amplifier. For the precision required at these data rates, the AM-to-PM conversion of a limiter is an ideal method for applying RJ.

Though not yet required in any released standards, expect to see random noise (RN) required in specifications as the industry gains more experience at 25+ Gb/s. RN also can be introduced by adding precision Gaussian noise to the signal but without a limiter.

Setting the vertical eye closure penalty (VECP) to the level in Table 2 is a multistep process. Optical VEC is given by

VECP = 10log[0MA]/[EH.sub.(2.5 x [10.sup.-3])]

where the eye height, EH(2.5x[10.sup.-3]), is the vertical eye opening defined at a BER. While conceptually cumbersome, EH(BER) is a more precise definition than average peak-to-peak voltage swing. It is equivalent to the vertical distance at the center of the eye between BER contours of 2.5x[10.sub.-3].

After setting VECP, the next step is to tune the J2 and J9 jitter levels, which indicate the properties of the jitter distribution. The high probability jitter, 99% of the distribution, is contained in J2, hence J2 is equivalent to the total jitter (TJ) defined at BER = 2.5x[10.sup.-3]. On the other hand, J9 indicates the low probability, RJ-dominated tails of the jitter distribution, the outer billionth; hence J9 is equivalent to TJ at BER = 2.5x [10.sup.-10]. Sinusoidal interference (amplitude modulation) is added to the signal until the J2 requirement is reached.

Testing Electrical Transmitters

Transmitter characteristics can be measured on either a sampling oscilloscope or BERT. In either case, a reference receiver is required with a golden PLL, such as a high-end clock recovery unit. Note that the transmitted signal amplitude specification is in terms of eye height EH(BER) while eye width is EW(BER).

Since electrical transmitters at these rates apply signal pre-emphasis to partially correct channel response, compliance test boards are inserted between the transmitter outputs and test equipment. Just as each specification has different requirements depending on application and length of transmission on PCB, compliance boards have different loss and frequency response profiles.

Testing the transmitter with intermediate pre-emphasis values is a good starting point. Introduce the compliance board, choose a trace that's about the minimum prescribed length, and optimize the transmitter pre-emphasis scheme. If the resulting pre-emphasis level is less than half that allowed, use a slightly longer trace. If it's much larger than half that allowed, try a slightly shorter trace.

Eye diagrams at these data rates, even after transmission across just a few centimeters of PCB, can be closed at the receiver, even with pre-emphasis. Accordingly, some specifications also require that the test equipment apply a continuous time linear equalization (CTLE) scheme. This way the interaction of transmitter pre-emphasis and minimal receiver equalization is included in the test. The CTLE typically is a single zero, two-pole filter that peaks at the Nyquist rate, [f.sub.data]/2.

Different specifications require different test patterns. For transmitter testing, a PRBS9 pattern usually is sufficient. Of course, all other system channels should be active so that crosstalk is included in the tests. Crosstalk aggressors should transmit different patterns, and the aggressors should be asynchronous.

With the compliance board in place and pre-emphasis optimized, configure the CTLE gain as defined by the spec, typically 1 dB to 3 dB, to produce the greatest EH(BER). If you're using an oscilloscope, collect at least 12 million samples; if you're using a BERT, acquire at least 4 million bits. The greater the statistical sample, the better.

EH([10.sub.-15]) is the vertical separation of the inner BER = [10.sub.15] contours at the center of the eye. Similarly, EW([10.sup.-15]) is the horizontal separation of the inner BER = [10.sup.-15] contours at the eye center. VEC is the ratio of the average voltage swing and eye height:

VEC = 20log[V.sub.avg swing]/[EH.sub.([10.sup.-15])]

Testing Electrical Receivers

Stressed receiver tolerance testing is meant to subject the receiver to the worst-case signal. If the receiver, including its internal equalization scheme, operates at or less than the prescribed BER, BER [less than or equal to] [10.sup.-12] for 100 GbE and 32GFC and BER [less than or equal to] [10.sup.-15] for OIF-CEI, then the receiver is compliant.

Each specification requires different levels and types of stress. Some only require SJ. Be sure to check the specification to which you are testing to guarantee that your test is compliant.

To configure the stressed signal, connect the compliance test board between the BERT's pattern generator output and error detector input. Then generate a PRBS31 test pattern; a long pattern with every permutation of 31 symbols to produce every imaginable bit trajectory. From there, you will need to apply other impairments such as DJ, crosstalk, sinusoidal interference, and RJ. To perform the test, assure that the receiver sees the signal you've configured, it's best to connect the receiver to the compliance board with the same cable used to set up the test.

If the receiver is capable of counting its own BER, you're ready to go. If not, connect the receiver output to the BERT error detector. If the receiver doesn't provide a clock output, you should use a clock recovery unit to time the error detector. If you don't have a clock recovery unit, you might be able to use the BERT data-rate clock since the output of the receiver has been retimed.

Apply the stressed signal to the receiver first with low-amplitude SJ applied above the roll-off frequency. If the receiver operates at or better than the specified BER with its equalization scheme enabled and optimized, continue testing across the SJ frequency-amplitude range to assure that the receiver can track low-frequency jitter with all other stresses applied. The receiver is compliant if it operates at or better than the specified BER across the SJ frequency range.

Diagnostic Tests

The difference between compliance and diagnostic tests is complexity. Compliance tests tend to include too many elements for straightforward interpretation. To determine which elements or components of a system might be causing problems, diagnostic tests should be strategically planned to probe specific weaknesses. They should build in complexity, test upon test, to find problems and determine margins.

If the transmitter fails, simplify test conditions by removing any test compliance boards and analyzing the transmitter output with as direct a connection as possible. Perform jitter and noise analysis. Analyze the breakdown as you apply more complex patterns, introduce increasing lengths of PCB, apply pre-emphasis, and turn on crosstalk aggressors. For each set of conditions, analyze eye diagrams, BER eye, BER contours, and the jitter and noise breakdown as shown in Figure 1. Similarly, when the receiver fails, you will need to investigate the receiver's response to each stress.

Summary

Signal transmission at 100 Gb/s is not simple, and many of the standards are still evolving. At 25+ Gb/s transmissions speed, the jitter budget has all but disappeared, and the industry is still building experience around transmitter and receiver testing at these speeds. Therefore, it is vital that engineers building 100G systems have a solid understanding of how analog waveforms relate to digital signal BERs and ensure they are measuring with test instrumentation featuring low intrinsic jitter and noise to maximize jitter budgets.

Acknowledgement

This article is adapted from Physical Layer Tests of 100 Gb/s Communications Systems, a Tektronix application note, 2012.

Editor's Note

The online version of this article provides additional information and graphics regarding this technology.

by Chris Loberg, Tektronix

About the Author

Chris Loberg is a senior technical marketing manager at Tektronix. He has held various positions with Tektronix during his more than 13 years with the company, including marketing manager for the Optical Business Unit. Previously, he was employed by Grass Valley Group and IBM. Loberg earned an M.B.A. in marketing from San Jose State University. Christopher, j.loberg@tektronix.com
COPYRIGHT 2013 NP Communications, LLC
No portion of this article can be reproduced without the express written permission from the copyright holder.
Copyright 2013 Gale, Cengage Learning. All rights reserved.

Article Details
Printer friendly Cite/link Email Feedback
Title Annotation:COMMUNICATIONS TEST
Author:Loberg, Chris
Publication:EE-Evaluation Engineering
Geographic Code:1USA
Date:Oct 1, 2013
Words:2768
Previous Article:Dealing with increased MRI field strength.
Next Article:Portable logic analyzers.
Topics:

Terms of use | Privacy policy | Copyright © 2021 Farlex, Inc. | Feedback | For webmasters |